 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| smsc ucs1002 revision 1.4 (07-16-13) datasheet datasheet product features UCS1002-1 programmable usb port power controller with charger emulation general description the ucs1002 provides a usb port power switch for precise control of up to 2.5 amperes continuous current with over-current limit (ocl), dynamic thermal management, latch or auto-recovery (low test current) fault handling, selectable active low or high enable, under- and over-voltage lockout, back-drive protection, and back-voltage protection. split supply support for vs and vdd is an option for low power in system standby states. this gives battery operated applications, like no tebook pcs, the ability to detect attachments from a sleep or off state. after the attach detection is flagged, the system can decide to wake up and/or provide charging. in addition to power switching and current limiting modes, the ucs1002 will aut omatically charge a wide variety of portable devices, including usb-if bc1.2, yd/t-1591 (2009), most apple ? and rim ? , and many others. nine preloaded charger emulation profiles maximize compatibility coverage of peripheral devices. as well, a customizable charger emulation profile is available to accommodate unique existing and future portable device handshaking / signature requirements. this custom profile uses a unique stimulus and response method referenced below.* the ucs1002 also provides current monitoring to allow intelligent management of syst em power and a battery full option for controlled delivery of current regardless of the host power state. this is especially important for battery operated applications that want to provide power in a standby and/or off state but do not want to drain the battery excessively. the ucs1002 is available in a 20-pin qfn 4 mm x 4 mm package. applications ? notebook and netbook computers ? tablets and e-book readers ? desktops and monitors ? docking stations and printers ? ac-dc wall adapters features ? port power switch with two current limit behaviors ? 2.9 v to 5.5 v source voltage range ? up to 2.5 a current with 55 m on resistance ? over-current trip or constant current limiting ? soft turn-on circuitry ? programmable current limit ? dynamic thermal management ? under- and over-voltage lockout ? back-drive, back-voltage protection ? latch or auto-recovery (low test current) fault handling ? selectable active high or low power switch enable ? bc1.2 vbus discharge port renegotiation function ? selectable / automatic cycling of usb data line charger emulation profiles ? customizable emulation prof ile uses a unique stimulus and response method useful for future profiles* ? supports charger emulation ? allows for active cables ? usb-if bc1.2 charging downstream port (cdp) & dedicated charging port (dcp) modes, yd/t-1591, and most apple and rim protocols standard; others as defined via the smbus 2.0 / i 2 c ? ? usb 2.0 compliant high-speed data switch (in pass- through and cdp modes) ? nine preloaded charger emulation profiles for maximum compatibility coverage of peripheral devices ? one custom programmable charger emulation profile for portable device support for fully host controlled charger emulation ? fault alert open-drain output ? self-contained current monitoring ? low power attach detection and open-drain a_det# pin ? ultra low power sleep state ? optional split supply support for vbus and vdd for low power in system standby states ? wake on attach usb ? smbus 2.0 / i 2 c communications ? supports block write and read ? multiple smbus addresses ? wide operating temperature range: -40 c to +85 c ? iec61000-4-2 8 / 15 kv esd immunity ? ul recognized and en/iec 60950-1 (cb) certified * unique technology covered under the following us patents pending: 13/109,446; 13/149,529; 13/173,287; 13/233,949; 13/157,282; 12/978,371; 13/232,965.
programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 2 smsc ucs1002 datasheet block diagram charger control, measurement, ocl interface, logic smclk / s0 smdata / latch a_det# alert# power switch temp pwr_en dpout dmout dpin vdd vs vbus dmin gnd usb 2.0 hs data switch & charger emulator comm_sel / ilim attach detector m1 m2 sel em_en vdd vdd uvlo, ovlo programmable usb port power controller with charger emulation datasheet smsc ucs1002 3 revision 1.4 (07-16-13) datasheet reel size is 4,000 pieces this product meets the halogen maximum concentration values per iec61249-2-21 for rohs compliance and environmen tal information, please visit www.smsc.com/rohs please contact your smsc sales representative fo r additional documentation related to this product such as application notes, anomaly sheets, and design guidelines. ordering number package features UCS1002-1-bp-tr 20 pin qfn 4mm x 4mm (rohs compliant) usb port power controller with charger emulation, 10w emulation support, attachment detection, current monitoring, current rationing, and programmable smbus address copyright ? 2013 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporat ion (?smsc?). product names and company na mes are the trademarks of their respective holders. the microchip name and logo, and the microchip logo are registered trademarks of microchip technology incorporated in the u.s.a . and other countries. smsc disclaims and excludes any and all warrant ies, including without limi tation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, a nd against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of wa rranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages. ordering information: programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 4 smsc ucs1002 datasheet table of contents chapter 1 terms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 chapter 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 chapter 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 3.1 esd & transient performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.1 human body model (hbm) performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.2 charged device model (cdm) performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.3 iec61000-4-2 performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 chapter 4 communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 smbus operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.1 system management bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.2 smbus and i 2 c compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2.3 smbus protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2.4 i 2 c protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3 stand-alone operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 chapter 5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 ucs1002 power states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.1 off state operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.2 sleep state operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1.3 detect state operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.4 active state operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.1.5 error state operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2 supply voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2.1 vdd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2.2 vs source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2.3 back-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.2.4 back-drive current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.2.5 under-voltage lockout on vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.2.6 over-voltage detection and lockout on vs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3 discrete input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.1 comm_sel / ilim input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.2 sel input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.3 m1, m2, and em_en inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3.4 pwr_en input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3.5 latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3.6 s0 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.4 discrete output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.4.1 alert# and a_det# output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.4.2 interrupt blanking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 chapter 6 usb high-speed data switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 usb high-speed data switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.1 usb-if high-speed compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 programmable usb port power controller with charger emulation datasheet smsc ucs1002 5 revision 1.4 (07-16-13) datasheet chapter 7 usb port power switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.1 usb port power switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2.1 current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2.2 short circuit output current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2.3 soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2.4 current limiting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.3 thermal management and voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.3.1 thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.4 vbus discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.5 battery full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.5.1 charge rationing interactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.6 fault handling mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.6.1 auto-recovery fault handlin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.6.2 latched fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 chapter 8 detect state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.1 device attach / removal dete ction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.2 vbus bypass switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3 attach detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.4 removal dete ction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 chapter 9 active state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1 active state overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.2 active mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.3 bc1.2 detection renegotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.4 data pass-through (no charger emulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.5 bc1.2 sdp (no charger emulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.6 bc1.2 cdp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.6.1 bc1.2 cdp charger emulation profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.7 bc1.2 dcp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.7.1 bc1.2 dcp charger emulation profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.8 dedicated charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.8.1 emulation reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.8.2 emulation cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.8.3 dce cycle retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.9 current limit mode associations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.10 no handshake. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.11 preloaded charger emulation profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.11.1 bc1.2 dcp charger emulation pr ofile within dce cycle . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.11.2 legacy 2 charger emulation profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 9.11.3 legacy 1, 3, 4, and 6 charger emulation profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.11.4 legacy 5 charger emulation profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 9.11.5 legacy 7 charger emulation profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 9.12 custom charger emulation profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 chapter 10 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 10.1 current measurement register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.2 total accumulated charge registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.3 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 6 smsc ucs1002 datasheet 10.3.1 other status - 0fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.3.2 interrupt status - 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.3.3 general status - 11h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.3.4 profile status 1 - 12h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.3.5 profile status 2 - 13h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.3.6 pin status register - 14h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.4 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.4.1 general configuration - 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.4.2 emulation configuration - 16h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.4.3 switch configuration - 17h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.4.4 attach detection configuration - 18 h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.4.5 high-speed switch configuration - 25h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.5 current limit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.6 charge rationing threshold registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.7 auto-recovery configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.8 ibus_chg configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.9 tdet_charge configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.10 preloaded emulation enable registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.10.1 bcs emulation enable - 20h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.10.2 legacy emulation enable - 21h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.11 preloaded emulation timeout configurat ion registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.11.1 bcs emulation timeout config - 22h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.11.2 legacy emulation timeout config 1 - 23h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.11.3 legacy emulation timeout config 2 - 24h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.12 preloaded emulation configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.12.1 applied charger emulation - 30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.12.2 preloaded emulation configuration registers 31h - 3bh . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.12.3 preloaded emulation stimulus x - config 1 - 31h, 35h, 39h . . . . . . . . . . . . . . . . . . . . . . . 92 10.12.4 bc1.2 emulation stimulus x - config 2 - 32h, 36h, 3ah . . . . . . . . . . . . . . . . . . . . . . . . . . 93 10.12.5 emulation stimulus x - config 3 - 33h, 37h, 3bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.12.6 emulation stimulus x - config 4 - 34h, 38h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.13 custom emulation configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.13.1 custom emulation configuration - 40h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.13.2 custom stimulus / response pair x - config 1 - 41h, 45h, 49h . . . . . . . . . . . . . . . . . . . 101 10.13.3 custom stimulus / response pair x - config 2 - 42h, 46h, 4ah . . . . . . . . . . . . . . . . . . . 101 10.13.4 custom stimulus / response pair x - config 3 - 43h, 47h, 4bh . . . . . . . . . . . . . . . . . . . 101 10.13.5 custom stimulus / response pair x - config 4 - 44h, 48h, 4ch . . . . . . . . . . . . . . . . . . . 102 10.14 current limiting behavior configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.14.1 applied current limiting behavior - 50h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.14.2 custom current limiting behavi or configuration - 51h . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.15 product id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.16 manufacturer id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.17 revision register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 chapter 11 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 chapter 12 typical operating curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 chapter 13 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 chapter 14 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 programmable usb port power controller with charger emulation datasheet smsc ucs1002 7 revision 1.4 (07-16-13) datasheet list of tables table 1.1 terms and abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2.1 ucs1002 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2.2 pin types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3.2 power dissipation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3.3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3.4 esd ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 4.1 ucs1002 communication mode and ilim selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 4.2 sel pin decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 4.3 protocol format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 4.4 write byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 4.5 read byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 4.6 send byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 4.7 receive byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 4.8 block write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 4.9 block read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 4.10 stand-alone fault and attach detection selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.1 power states control settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 7.1 charge rationing behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 7.2 charge rationing reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 7.3 effects of changing rationing behavior after th reshold reached . . . . . . . . . . . . . . . . . . . . . 55 table 9.1 active mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 9.2 current limit mode options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 10.1 register set in hexadecimal order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 10.2 current measurement register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 10.3 total accumulated charge registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 10.4 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 10.5 em_step bit decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 10.6 pwr_state bit decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 10.7 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 10.8 em_reset_time bit decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 10.9 discharge time options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 10.10attach / removal detection thresh old options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 10.11current limit register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 10.12ilim_sw bit decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 10.13charge rationing threshold registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 10.14auto-recovery configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 10.15t cycle options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 10.16trst_sw options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 10.17vtst_sw options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 10.18ibus_chg configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 10.19tdet_charge configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 table 10.20dc_temp_set bit decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 10.21det_charge_set bit decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 10.22preloaded emulation enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 10.23preloaded emulation timeout conf iguration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 10.24x_em_timeout bit decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 10.25preloaded emulation configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 0 table 10.26applied emulation selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 10.27stimulus delay time options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 8 smsc ucs1002 datasheet table 10.28stimulus options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 10.29stimulus response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 10.30response magnitude meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 10.31voltage divider minimum impedance options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 10.32stimulus response resistor options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 10.33stimulus response voltage options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 10.34pull-down magnitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 10.35stimulus threshold values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 10.36voltage divider ratio options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 10.37custom emulation configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 10.38current limit behavior configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 10.39v bus_min threshold options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 10.40i bus_r2min threshold options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 10.41product id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 10.42manufacturer id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 10.43revision register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 14.1 customer revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 programmable usb port power controller with charger emulation datasheet smsc ucs1002 9 revision 1.4 (07-16-13) datasheet list of figures figure 2.1 ucs1002 pin diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3.1 usb rise time / fall time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 3.2 description of dc terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4.1 smbus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 5.1 ucs1002 full-featured system configuration (smb us control) . . . . . . . . . . . . . . . . . . . . . 34 figure 5.2 ucs1002 system configuration (charger em ulation, no smbus, with usb host) . . . . . . . 35 figure 5.3 ucs1002 system configuration (no smbus, no charger emulation) . . . . . . . . . . . . . . . . . 36 figure 5.4 ucs1002 system configuration (no smbus, no usb host, with charge r emulation). . . . . 37 figure 5.5 wake timing via external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 5.6 wake via smbus read with s0 = ?0? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 7.1 trip current limiting operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 7.2 constant current limiting (varia ble slope) operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 7.3 error recovery timing (short circuit example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 8.1 detect state vbus biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 11.1 ucs1002 package view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 11.2 ucs1002 package dimensions and notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 12.1 usb-if high-speed eye diagram (without data switch ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 12.2 usb-if high-speed eye diagram (with data switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 12.3 short applied after power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 12.4 power up into a short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 12.5 internal power switch short resp onse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 12.6 vbus discharge behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 12.7 data switch off isolation vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 12.8 data switch bandwidth vs. freque ncy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 12.9 data switch on resist ance vs. temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 12.10power switch on resistance vs . temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 figure 12.11r dcp_res resistance vs.temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 12.12power switch on / off time vs. temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 12.13vs over-voltage threshold vs. te mp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 12.14vs under voltage threshold vs. temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 09 figure 12.15detect state vbus vs. ibus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 12.16trip current limit operation vs. temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 12.17ibus measurement accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 12.18active state current vs. temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 12.19detect state current vs. temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 12.20sleep state current vs. temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 10 smsc ucs1002 datasheet chapter 1 terms and abbreviations application note: the m1, m2, pwr_en, and em_en pins each have configuration bits ( programmable usb port power controller with charger emulation datasheet smsc ucs1002 11 revision 1.4 (07-16-13) datasheet dynamic thermal management the ucs1002 automatically adjusts port power switch limits and modes to lower internal power dissipation when the thermal regula tion temperature value is approached. enumeration a usb-specific term that indicates that a host is detecting and identifying usb devices. handshake application of a charger emulation profile that r equires a response. two-way communication between the ucs1002 and the portable device. hbm human body model. hsw high-speed switch. i bus_r2min current limiter mode boundary. ilim the ibus current threshold used in current limiting. in trip mode, when ilim is reached, the port power switch is opened. in constant current mode, when the current exceeds ilim, operation continues at a reduc ed voltage and increased current; if vbus voltage drops below v bus_min , the port power switch is opened. legacy usb devices that require non-bc1.2 signatures be applied on the dpout and dmout pins to enable charging. ocl over-current limit. por power-on reset. portable device usb device attached to the usb port. power thief a usb device that does not follow th e handshaking conventions of a bc1.2 device or legacy devices and draws current immediately upon receiving power (i.e., a usb book light, portable fan, etc). removal detection a removal detection event occurs wh en the current load on the vbus pin drops to less than i rem_qual for longer than t rem_qual . removal the physical removal of a portable device from a usb port that the ucs1002 is controlling. response an action, usually in response to a st imulus, in charger emulation performed by the ucs1002 device via the usb data lines. sdp or usb-if sdp standard downstream port. the co mbination of the ucs1002 high-speed switch being closed with an upstream usb host present comp rises a bc1.2 sdp. this enables a bc1.2 compliant portable device to simultaneously draw current up to 0.5 a while data communication is active. signature application of a charger emulation profile without wa iting for a response. one-way communication from the ucs1002 to the portable device. stand-alone mode indicates that the co mmunications protocol is not acti ve and all communications between the ucs1002 and a controller are done via t he external pins only (m1, m2, em_en, pwr_en, s0, and latch as inputs and alert# and a_det# as outputs). stimulus an event in charger emulation detected by the ucs1002 device via the usb data lines. table 1.1 terms and abbreviations (continued) term / abbreviation description programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 12 smsc ucs1002 datasheet chapter 2 pin description the pin types are described in table 2.2 . all pins are 5 v tolerant. figure 2.1 ucs1002 pin diagram table 2.1 ucs1002 pin description pin number pin name pin function pin type if pin not used connection 1 m1 active mode selector input #1 di connect to ground or vdd (see note 2.3 ) 2 m2 active mode selector input #2 di connect to ground or vdd (see note 2.3 ) 3 vbus1 voltage output from power switch. these pins must be tied together. hi-power, aio note 2.1 leave open 4 vbus2 m2 1 2 3 4 6 7 8 9 em_en m1 5 10 15 14 13 12 20 19 18 17 pwr_en comm_sel / ilim vbus1 vbus2 vs2 vdd dpin smclk / s0 a_det# dpout sel dmout smdata / latch dmin alert# gnd vs1 11 16 gnd flag ucs1002 20-qfn 4mm x 4mm programmable usb port power controller with charger emulation datasheet smsc ucs1002 13 revision 1.4 (07-16-13) datasheet 5 comm_sel / ilim comm_sel - selects smbus address or stand-alone mode of operation aio n/a ilim - selects the maximum current limit at power-up 6 sel selects whether pwr_en is active high or active low and determines the smbus address aio n/a 7 vs1 voltage input to power switch. these pins must be tied together. hi-power, aio connect to ground 8 vs2 9 vdd main power supply input for chip functionality power n/a 10 pwr_en port power switch enable input. polarity determined by sel pin. di connect to ground or vdd (see note 2.3 ) 11 smdata / latch smdata - smbus data input/output (requires pull-up resistor) diod n/a latch - in stand-alone mode, latch / auto-recovery fault handling mechanism selection input di 12 smclk / s0 smclk - smbu s clock input (requires pull-up resistor) di n/a s0 - in stand-alone mode, enables attach / removal detection feature 13 alert# active low error event output flag (requires pull-up resistor) od connect to ground 14 dpin usb data input (plus) aio connect to ground or ground through a resistor 15 dmin usb data input (minus) aio connect to ground or ground through a resistor 16 dmout usb data output (minus) aio (see note 2.2 ) connect to ground 17 dpout usb data output (plus) aio (see note 2.2 ) connect to ground 18 a_det# active low attach detection output flag (requires pull-up resistor) od connect to ground 19 em_en active mode selector input di connect to ground or vdd (see note 2.3 ) table 2.1 ucs1002 pin description (continued) pin number pin name pin function pin type if pin not used connection programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 14 smsc ucs1002 datasheet note 2.1 total leakage current from pins 3 and 4 (vbus) to ground must be less than 100 a for proper attach / removal detection operation. note 2.2 it is recommended to use 2 m pull-down resistors on the dpout pin and / or dmout pin if a portable device stimulus is expected when using the custom charger emulation profile with the high-speed data switch open. the 2 m value is based on bc1.1 impedance characteristics for dedicated charging ports. note 2.3 to ensure operation, the pwr_en pin must be enabled, as determined by the sel pin decode, when it is not driven by an external device. furthe rmore, one of the m1, m2, or em_en pins must be connected to vdd if all th ree are not driven from an external device. if the pwr_en is disabled or all of the m1 , m2, and em_en are connected to ground, the ucs1002 will remain in the sleep or detect state unless activated via the smbus. 20 gnd ground power n/a bottom pad gnd flag thermal connection to ground plane thermal pad n/a table 2.2 pin types pin type description power this pin is used to supply power or ground to the device. hi-power this pin is a high current pin. aio analog input / output - this pin is used as an i/o for analog signals. di digital input - this pin is used as a digital input. diod open-drain digital input / output - this pin is bidirectional. it is open-drain and requires a pull- up resistor. od open-drain digital output - used as a digita l output. it is open-drain and requires a pull-up resistor. table 2.1 ucs1002 pin description (continued) pin number pin name pin function pin type if pin not used connection programmable usb port power controller with charger emulation datasheet smsc ucs1002 15 revision 1.4 (07-16-13) datasheet chapter 3 electrical specifications note: stresses above those listed could cause perman ent damage to the ucs1002. this is a stress rating only and functional operation of the ucs1002 at any other condition above those indicated in the operation sections of this specification is not implied. note 3.1 a high k board uses a thermal via design with the thermal landing soldered to the pcb ground plane with 0.3 mm (12 mil) diameter vias in a 3x3 matrix (9 total) at 0.5 mm (20 mil) pitch. the board is multi-layer with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom. a low k boar d is a two layer board without thermal via design with 2-ounce copper traces on the top and bottom. table 3.1 absolute maximum ratings voltage on vdd, vs, and vbus pins -0.3 to 6 v pullup voltage (v pullup ) -0.3 to vdd + 0.3 data switch current (i hsw _ on ), switch on 50 ma port power switch curr ent internally limited data switch pin voltage to ground (dpout, dpin, dmout, dmin); (vdd powered or unpowered) -0.3 to vdd + 0.3 v differential voltage across open data switch (dpout - dpin, dmout - dmin, dpin - dpout, dmin - dmout) vdd v voltage on any other pin to ground -0.3 to vdd + 0.3 v current on any other pin 10 ma package power dissipation see ta b l e 3 . 2 operating ambient temperature range -40 to 125 c storage temperature range -55 to 150 c table 3.2 power dissipation summary board pkg jc ja derating factor above 25 c ta < 25 c power rating ta = 70 c power rating ta = 85 c power rating high k (see note 3.1 ) 20-pin qfn 4 mm x 4 mm 6c / w 41 c / w 24.4 mw / c 2193 mw 1095 mw 729 mw low k (see note 3.1 ) 20-pin qfn 4 mm x 4 mm 6c / w 60 c / w 16.67 mw / c 1498 mw 748 mw 498 mw programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 16 smsc ucs1002 datasheet table 3.3 electrical specifications vdd = 4.5 v to 5.5 v, vs = 2.9 v to 5.5 v, v pullup = 3v to 5.5v, t a = -40 c to 85 c all typical values at vdd = vs = 5 v, t a = 27 c unless otherwise noted. characteristic symbol min typ max unit conditions power and interrupts - dc supply voltage vdd 4.5 5 5.5 v see note 3.2 source voltage vs 2.9 5 5.5 v see note 3.2 supply current in active (i dd_active + i vs_act ) i active 650 750 a average current ibus = 0 ma supply current in sleep (i dd_sleep + i vs_sleep ) i sleep 5 15 a average current v pullup < vdd supply current in detect (i dd_detect + i vs_detect ) i detect 185 220 a average current no portable device attached. power-on reset vs low threshold v s_uvlo 2.5 2.7 v vs voltage increasing vs low hysteresis v s_uvlo_hyst 100 mv vs voltage decreasing vdd low threshold v dd_th 4 4.4 v vdd voltage increasing vdd low hysteresis v dd_th_hyst 500 mv vdd voltage decreasing i/o pins - smclk, smdata, em_en, m1, m2 , pwr_en, alert#, a_det# - dc parameters output low voltage v ol 0.4 v i sink_io = 8 ma smdata, alert#, a_det# input high voltage v ih 2.0 v pwr_en, em_en, m1, m2, smdata, smclk input low voltage v il 0.8 v pwr_en, em_en, m1, m2, em_en, smdata, smclk leakage current i leak 5 a powered or unpowered v pullup <= vdd t a < 85 c interrupt pins - ac parameters alert#, a_det# pin blanking time t blank 25 ms alert# pin interrupt masking time t mask 5ms programmable usb port power controller with charger emulation datasheet smsc ucs1002 17 revision 1.4 (07-16-13) datasheet smbus / i 2 c timing input capacitance c in 5pf clock frequency f smb 10 400 khz spike suppression t sp 50 ns bus free time stop to start t buf 1.3 s start setup time t su:sta 0.6 s start hold time t hd:sta 0.6 s stop setup time t su:sto 0.6 s data hold time t hd:dat 0 s when transmitting to the master data hold time t hd:dat 0.3 s when receiving from the master data setup time t su:dat 0.6 s clock low period t low 1.3 s clock high period t high 0.6 s clock / data fall time t fall 300 ns min = 20+0.1c load ns clock / data rise time t rise 300 ns min = 20+0.1c load ns capacitive load c load 400 pf per bus line timeout t timeout 25 35 ms disabled by default idle reset t idle_reset 350 s disabled by default. high-speed data switch high-speed data switch - dc parameters switch leakage current i hsw_off 0.5 a switch open - dpin to dpout, dmin to dmout, or all four pins to ground. vdd < vs. charger resistance r chg 2m dpout or dmout to vbus or ground, see figure 3.2 bc1.2 dcp charger emulation active table 3.3 electrical specifications (continued) vdd = 4.5 v to 5.5 v, vs = 2.9 v to 5.5 v, v pullup = 3v to 5.5v, t a = -40 c to 85 c all typical values at vdd = vs = 5 v, t a = 27 c unless otherwise noted. characteristic symbol min typ max unit conditions programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 18 smsc ucs1002 datasheet on resistance r on_hsw 2 switch closed, vdd = 5 v test current = 8 ma, test voltage = 0.4 v, see figure 3.2 on resistance r on_hsw_1 5 switch closed, vdd = 5 v, test current = 8 ma, test voltage = 3.0 v, see figure 3.2 delta on resistance r on_hsw 0.3 switch closed, vdd = 5 v i tst = 8 ma, v tst = 0 to 1.5 v, see figure 3.2 high-speed data switch - ac parameters dp, dm capacitance to ground c hsw_on 4 pf switch closed vdd = 5 v dp, dm capacitance to ground c hsw_off 2 pf switch open vdd = 5 v turn off time t hsw_off 400 s time from state control (em_en, m1, m2) switch on to switch off, r term = 50 , c load = 5 pf turn on time t hsw_on 400 s time from state control (em_en, m1, m2) switch off to switch on, r term = 50 , c load = 5 pf propagation delay t pd 0.25 ns r term = 50 , c load = 5 pf propagation delay skew t pd 25 ps r term = 50 , c load = 5 pf rise/fall time t f/r 10 ns r term = 50 , c load = 5 pf dp - dm crosstalk x talk -40 db r term = 50 , c load = 5 pf off isolation o irr -30 db r term = 50 , c load = 5 pf f = 240 mhz -3db bandwidth bw 1100 mhz r term = 50 , c load = 1.5 pf v dpout = v dmout = 350 mv dc total jitter t j 200 ps r term = 50 , c load = 5 pf, rise time = fall time = 500 ps at 480 mbps (prbs = 2 15 - 1) skew of opposite transitions of the same output t sk(p) 20 ps r term = 50 , c load = 5 pf table 3.3 electrical specifications (continued) vdd = 4.5 v to 5.5 v, vs = 2.9 v to 5.5 v, v pullup = 3v to 5.5v, t a = -40 c to 85 c all typical values at vdd = vs = 5 v, t a = 27 c unless otherwise noted. characteristic symbol min typ max unit conditions programmable usb port power controller with charger emulation datasheet smsc ucs1002 19 revision 1.4 (07-16-13) datasheet port power switch port power switch - dc parameter over-voltage lockout v s_ov 6v on resistance r on_psw 55 65 m 4.75 v < vs < 5.25 v vs leakage current i leak_vs 2.2 5 a sleep state into vs pin back-voltage protection threshold v bv_th 150 mv vbus > vs vs > v s_uvlo back-drive current i bd_1 0 3 a vdd < v dd_th , any powered power pin to any unpowered power pin. current out of unpowered pin. i bd_2 0 2 a vdd > v dd_th , any powered power pin to any unpowered power pin, except for vdd to vbus in detect power state and vs to vbus in active power state. current out of unpowered pin. selectable current limits i lim1 450 467 500 ma ilim resistor = 0 or 47 k (500 ma setting) i lim2 810 839 900 ma ilim resistor = 10 k or 56 k (900 ma setting) i lim3 900 932 1000 ma ilim resistor = 12 k or 68 k (1000 ma setting) i lim4 1080 1112 1200 ma ilim resistor = 15 k or 82 k (1200 ma setting) i lim5 1350 1385 1500 ma ilim resistor = 18 k or 100 k (1500 ma setting) i lim6 1620 1702 1800 ma ilim resistor = 22 k or 120 k (1800 ma setting) i lim7 1800 1892 2000 ma ilim resistor = 27 k or 150 k (2000 ma setting) i lim8 2250 2355 2500 ma ilim resistor = 33 k or vdd (2500 ma setting) pin wake time t pin_wake 3ms table 3.3 electrical specifications (continued) vdd = 4.5 v to 5.5 v, vs = 2.9 v to 5.5 v, v pullup = 3v to 5.5v, t a = -40 c to 85 c all typical values at vdd = vs = 5 v, t a = 27 c unless otherwise noted. characteristic symbol min typ max unit conditions programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 20 smsc ucs1002 datasheet smbus wake time t smb_wake 4ms idle sleep time t idle_sleep 200 ms thermal regulation limit t reg 110 c die temperature at which current limit will be reduced thermal regulation hysteresis t reg_hyst 10 c hysteresis for t reg functionality. temperature must drop by this value before ilim value restored to normal operation thermal shutdown threshold t tsd 135 c die temperature at which port power switch will turn off thermal shutdown hysteresis t tsd_hyst 35 c after shutdown due to t tsd being reached, die temperature drop required before port power switch can be turned on again auto-recovery test current i test 190 ma portable device attached, vbus = 0 v, die temp < t tsd auto-recovery test voltage v test 750 mv portable device attached, vbus = 0 v before application, die temp < t tsd programmable, 250 - 1000 mv, default listed discharge impedance r discharge 100 port power switch - ac parameters turn on delay t on_psw 0.75 ms pwr_en active toggle to switch on time, vbus discharge not active turn off time t off_psw_ina 0.75 ms pwr_en inactive toggle to switch off time c bus = 120 f turn off time t off_psw_err 1 ms over-current error, vbus min error, or discharge error to switch off c bus = 120 f turn off time t off_psw_err 100 ns tsd or back-drive error to switch off c bus = 120 f vbus output rise time t r_bus 1.1 ms measured from 10% to 90% of vbus, c load = 220 f ilim = 1.0 a table 3.3 electrical specifications (continued) vdd = 4.5 v to 5.5 v, vs = 2.9 v to 5.5 v, v pullup = 3v to 5.5v, t a = -40 c to 85 c all typical values at vdd = vs = 5 v, t a = 27 c unless otherwise noted. characteristic symbol min typ max unit conditions programmable usb port power controller with charger emulation datasheet smsc ucs1002 21 revision 1.4 (07-16-13) datasheet soft turn on rate i bus / t 100 ma / s temperature update time t dc_temp 200 ms programmable 200 - 1600 ms, default listed short circuit response time t short_lim 1.5 s time from detection of short to current limit applied. no c bus applied short circuit detection time t short 6 ms time from detection of short to port power switch disconnect and alert# pin assertion. latched mode cycle time t ul 7 ms from pwr_en edge transition from inactive to active to begin error recovery auto-recovery mode cycle time t cycle 25 ms time delay before error condition check programmable 15-50 ms, default listed auto-recovery delay t rst 20 ms portable device attached, vbus must be > v test after this time programmable 10-25 ms, default listed discharge time t discharge 200 ms amount of time discharge resistor applied programmable 100-400 ms, default listed port power switch operation with trip mode current limiting region 2 current keep- out i bus_r2min 0.1 a minimum vbus allowed at output v bus_min 2.0 v port power switch operation with co nstant current limiting (variable slope) region 2 current keep- out i bus_r2min 1.5 a minimum vbus allowed at output v bus_min 2.0 v port power switch operation with custom current limiting region 2 current keep- out i bus_r2min 0.1 a programmable from 100 ma to 1.8 a. default value listed. table 3.3 electrical specifications (continued) vdd = 4.5 v to 5.5 v, vs = 2.9 v to 5.5 v, v pullup = 3v to 5.5v, t a = -40 c to 85 c all typical values at vdd = vs = 5 v, t a = 27 c unless otherwise noted. characteristic symbol min typ max unit conditions programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 22 smsc ucs1002 datasheet minimum vbus allowed at output v bus_min 2.0 v programmable from 1.5 v to 2.25 v. default value listed. current measurement - dc current measurement range i bus_m 6.4 2500 ma range (see note 3.3 ) reported current measurement resolution i bus_m 9.76 ma 1 lsb current measurement accuracy 2 % ilim not exceeded current measurement - ac sampling rate 500 s charge rationing - dc accumulated current measurement accuracy 4.5 % charge rationing - ac current measurement update time t pcycle 1s attach / removal detection vbus bypass - dc on resistance r on_byp 50 leakage current i leak_byp 3 a switch off current limit i det_chg / i bus_byp 2 ma vdd = 5 v and vbus> 4.75 v attach / removal detection - dc attach detection threshold i det_qual 800 a programmable 200-1000 a, default listed primary removal detection threshold i rem_qual_act 700 a programmable 100-900 a, default listed active power state i rem_qual_det 800 a programmable 200-1000 a, default listed detect power state (see section 8.4 ) table 3.3 electrical specifications (continued) vdd = 4.5 v to 5.5 v, vs = 2.9 v to 5.5 v, v pullup = 3v to 5.5v, t a = -40 c to 85 c all typical values at vdd = vs = 5 v, t a = 27 c unless otherwise noted. characteristic symbol min typ max unit conditions programmable usb port power controller with charger emulation datasheet smsc ucs1002 23 revision 1.4 (07-16-13) datasheet attach / removal detection - ac attach detection time t det_qual 100 ms time from attach to a_det# assert . removal detection time t rem_qual 1000 ms allowed charge time t det_charge 800 ms c bus = 500 f max programmable 200-2000 ms, default listed charger emulation profile general emulation - dc charging current threshold i bus_chg 9.76 ma default charging current threshold range i bus_chg_rng 9.76 155 ma programmable, all typical dp-dm shunt resistor value r dcp_res 200 connected between dpout and dmout 0 v < dpout = dmout < 3v response magnitude (voltage divider option min resistance range) sx_rxmag_ dvdr 93 200 k programmable, all mins resistor ratio range (voltage divider option) sx_ratio 0.25 0.66 v / v programmable, all typical resistor ratio accuracy (voltage divider option) sx_ratio_ acc 0.5 % average over range response magnitude (resistor option range) sx_rxmag_ res 1.8 150 k programmable, all typical internal resistor tolerance (resistor option) sx_rxmag_ res_acc 10 % average over range response magnitude (voltage option range) sx_rxmag_ volt 0.4 2.2 v programmable, all typical voltage option accuracy sx_rxmag_ volt_acc 1 % no load average over range voltage option accuracy sx_rxmag_ volt_acc_ 150 -6 % 150 a load average over range voltage option accuracy sx_rxmag_ volt_acc_ 250 -10 % 250 a load average over range table 3.3 electrical specifications (continued) vdd = 4.5 v to 5.5 v, vs = 2.9 v to 5.5 v, v pullup = 3v to 5.5v, t a = -40 c to 85 c all typical values at vdd = vs = 5 v, t a = 27 c unless otherwise noted. characteristic symbol min typ max unit conditions programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 24 smsc ucs1002 datasheet note 3.2 for split supply systems using the attach de tection feature, vs must not exceed vdd + 150 mv. note 3.3 the current measurement full scale range maximum value is 2.5 a. however, the ucs1002 cannot report values above ilim (if i bus_r2min < ilim) or above i bus_r2min (if i bus_r2min > ilim and ilim < 1.5 a). voltage option output sx_rxmag_ volt_bc 0.5 v dmout = 0.6 v 250 a load response magnitude (zero volt option range) sx_pupd 10 150 a sx_rxmag_volt = 0 programmable, all typical pull-down current accuracy sx_pupd _acc_3p6 5 % dpout or dmout = 3.6 v compliance voltage pull-down current sx_pupd _acc_bc 50 a setting = 100 a dpout or dmout = 0.15 v compliance voltage stimulus voltage threshold range sx_th 0.3 2.2 v programmable, all typical stimulus voltage accuracy sx_th_ acc 2 % average over range stimulus voltage accuracy sx_th_acc_ bc 0.25 v at sx_th = 0.3 v stimulus voltage hysteresis sx_th_hyst 40 mv voltage falling general emulation - ac emulation reset time t em_reset 50 ms default emulation reset time range t em_reset_ rng 50 175 ms programmable, all typical emulation timeout range t em_ timeout 0.8 12.8 s programmable, 0.8 s to 12.8 s, all typical stimulus delay, sx_td range t stim_del 0 100 ms programmable, all typical emulation delay t res_em 0.5 s time from set impedance to impedance appears on dp / dm table 3.3 electrical specifications (continued) vdd = 4.5 v to 5.5 v, vs = 2.9 v to 5.5 v, v pullup = 3v to 5.5v, t a = -40 c to 85 c all typical values at vdd = vs = 5 v, t a = 27 c unless otherwise noted. characteristic symbol min typ max unit conditions programmable usb port power controller with charger emulation datasheet smsc ucs1002 25 revision 1.4 (07-16-13) datasheet figure 3.1 usb rise time / fall time measurement figure 3.2 description of dc terms dpin dpout r chg v bus v tst r chg i tst dmin r chg v bus v tst r chg i tst dmout programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 26 smsc ucs1002 datasheet 3.1 esd & transient performance application note: depending on the level of esd protection requir ed by the application, external protection devices may be required. the datasheet esd levels were reached using external devices and standard usb-a connectors; refer to th e evb schematic and reference design for details. note 3.4 operational classification b indicates that during and immediately after an esd event, anomalous behavior may occur; however, it is non-damaging and the device is self- recovering. all iec testing is performed using an smsc evaluation board. note 3.5 operational classification a indicates that during and immediately after an esd event no anomalous behavior will occur. all iec testi ng is performed using an smsc evaluation board. 3.1.1 human body model (hbm) performance hbm testing verifies the ability to withstand es d strikes like those that occur during handling and manufacturing and is done without power applied to the ic. to pass the test, the device must have no change in operation or performance due to the event. 3.1.2 charged device model (cdm) performance cdm testing verifies the ability to withstand esd strikes like those that occur during handling and assembly with pick and place style machinery and is done without power applied to the ic. to pass the test, the device must have no change in operation or performance due to the event. 3.1.3 iec61000-4-2 performance the iec61000-4-2 esd specif ication is an international standard that addresses system-level immunity to esd strikes while the end equipment is operational. these tests are performed while the device is powered. table 3.4 esd ratings esd spec rating or value en / iec61000-4-2 (dpout, dmout pins) air gap, operational classification b (see note 3.4 ) level 4 (15 kv) en / iec61000-4-2 (dpout, dmout pins) direct contact, operational classification b (see note 3.4 ) level 4 (8 kv) en / iec61000-4-2 (vbus, gnd pins) air gap, operational classification a (see note 3.5 ) level 4 (15 kv) en / iec61000-4-2 (vbus, gnd pins) direct contact, operational classification a (see note 3.5 ) level 4 (8 kv) human body model (jedec jesd22-a114) - all pins 8 kv charged device model (jedec jesd22-c101) - all pins 500 v programmable usb port power controller with charger emulation datasheet smsc ucs1002 27 revision 1.4 (07-16-13) datasheet chapter 4 communications 4.1 operating mode the ucs1002 can operate in smbus mode (see section 4.2, "smbus operating mode" ) or stand- alone mode (see section 4.3, "stand-al one operating mode" ). the resistor on the comm_sel / ilim pin determines operating mode and the hardware-set ilim setting, as shown in ta b l e 4 . 1 . unless connected to gnd or vdd, the resistors in ta b l e 4 . 1 are pull-down resistors. application note: if it is necessary to connect the comm_sel / ilim pin to vdd via a pull-up resistor, it is recommended that this resistor value not exceed 100 k . table 4.1 ucs1002 communication mode and ilim selection selection resistor 5% ilim setting communications mode gnd 500 ma smbus - see section 4.2.1.2 10 k pull-down 900 ma smbus - see section 4.2.1.2 12 k pull-down 1000 ma smbus - see section 4.2.1.2 15 k pull-down 1200 ma smbus - see section 4.2.1.2 18 k pull-down 1500 ma smbus - see section 4.2.1.2 22 k pull-down 1800 ma smbus - see section 4.2.1.2 27 k pull-down 2000 ma smbus - see section 4.2.1.2 33 k pull-down 2500 ma smbus - see section 4.2.1.2 47 k pull-down 500 ma stand-alone mode 56 k pull-down 900 ma stand-alone mode 68 k pull-down 1000 ma stand-alone mode 82 k pull-down 1200 ma stand-alone mode 100 k pull-down 1500 ma stand-alone mode 120 k pull-down 1800 ma stand-alone mode 150 k pull-down 2000 ma stand-alone mode vdd (if a pull-up resistor is used, its value must not exceed 100 k .) 2500 ma stand-alone mode programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 28 smsc ucs1002 datasheet 4.2 smbus operating mode when the comm_sel / ilim pin is connected to dire ctly to ground or though a pull-down resistor with a value of 33k or below as listed in table 4.1, "ucs1002 communication mode and ilim selection" , the ucs1002 communicates via the smbus or i 2 c communications protocols. application note: upon power-up, the ucs1002 will not respond to any smbus communications for 5.5 ms. after this time, full functionality is available. application note: when in the sleep state, the first smbus read command sent to the ucs1002 device address will wake it. any data sent to the ucs1002 will be ignored and any data read from the ucs1002 should be considered invalid. the ucs1002 will be fully functional 3 ms after this first read command is sent. see section 5.1.2 . 4.2.1 system management bus in smbus mode, the ucs 1002 communicates with a host controlle r, such as an smsc sio. the smbus is a two-wire serial communication prot ocol between a computer host and its peripheral devices. a detailed timing diagram is shown in figure 4.1 . stretching of the smclk signal is supported; however, the ucs1002 will not stretch the clock signal. 4.2.1.1 smbus start bit the smbus start bit is defined as a transition of th e smbus data line from a logic ?1? state to a logic ?0? state while the smbus clock line is in a logic ?1? state. 4.2.1.2 smbus address and rd / wr bit the smbus address byte consists of the 7-bit client address followed by the rd / wr indicator bit. if this rd / wr bit is a logic ?0?, the smbus host is writi ng data to the client device. if this rd / wr bit is a logic ?1?, the smbus host is re ading data from the client device. the smbus address is determined based on the resistor connected on the sel pin as shown in table 4.2 . application note: if it is necessary to connect the sel pin to vdd via a resistor, the pull-up resistor may be any value up to 100 k . figure 4.1 smbus timing diagram smdata smclk t buf p s s - start condition p - stop condition p s t high t low t hd:sta t su:sto t hd:sta t hd:dat t su:dat t su:sta t fall t rise programmable usb port power controller with charger emulation datasheet smsc ucs1002 29 revision 1.4 (07-16-13) datasheet 4.2.1.3 smbus data bytes all smbus data bytes are sent most significant bi t first and composed of 8- bits of information. 4.2.1.4 smbus ack and nack bits the smbus client will acknowledge all data bytes that it receives. this is done by the client device pulling the smbus data line low after the 8th bit of eac h byte that is transmitted. this applies to both the write byte and block write protocols. the host will nack (not acknowledge) the last data byte to be received from the client by holding the smbus data line high after the 8th data bit has b een sent. for the block read protocol, the host will ack each data byte that it rece ives except the last data byte. 4.2.1.5 smbus stop bit the smbus stop bit is defined as a transition of the smbus data line from a logic ?0? state to a logic ?1? state while the smbus clock line is in a logic ?1? state. when the ucs1002 detects an smbus stop table 4.2 sel pin decode resistor (5%) pwr_en polarity smbus address gnd active low 1010_111(r/w ) 10 k pull-down active low 1010_110(r/w ) 12 k pull-down active low 1010_101(r/w ) 15 k pull-down active low 1010_100(r/w ) 18 k pull-down active low 0110_000(r/w ) 22 k pull-down active low 0110_001(r/w ) 27 k pull-down active low 0110_010(r/w ) 33 k pull-down active low 0110_011(r/w ) 47 k pull-down active high 0110_011(r/w ) 56 k pull-down active high 0110_010(r/w ) 68 k pull-down active high 0110_001(r/w ) 82 k pull-down active high 0110_000(r/w ) 100 k pull-down active high 1010_100(r/w ) 120 k pull-down active high 1010_101(r/w ) 150 k pull-down active high 1010_110(r/w ) vdd (if a pull-up resistor is used, its value must not exceed 100 k .) active high 1010_111(r/w ) programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 30 smsc ucs1002 datasheet bit, and it has been communicating with the smbus pr otocol, it will reset its client interface and prepare to receive further communications. 4.2.1.6 smbus timeout and idle reset the ucs1002 includes an smbus timeout feature. if the clock is held at logic ?0? for t timeout , the device can timeout and reset the smbus interface. the smbus interface can also reset if both the clock and data lines are held at a logic ?1? for t idle_reset . communication is restored with a start condition. this functionality defaults to disabled and can be enabled by clearing the dis_to bit in the emulation configuration register (see section 10.4.2, "emulati on configuration - 16h" ). 4.2.2 smbus and i 2 c compatibility the major differences between smbus and i 2 c devices are highlighted here. for more information, refer to the smbus 2.0 and i 2 c specifications. 1. ucs1002 supports i 2 c fast mode at 400 khz. this cove rs the smbus max time of 100 khz. 2. minimum frequency for smbus communications is 10 khz. 3. the smbus client protocol will reset if the clo ck is held at a logic ?0? for longer than 30 ms. this timeout functionality is disabled by default in the ucs1002 and can be enabled by clearing the dis_to bit. i 2 c does not have a timeout. 4. except when operating in sleep, the smbus cl ient protocol will reset if both the clock and data lines are held at a logic ?1? for longer than 200 s (idle condition). this function is disabled by default in the ucs1002 and can be enabled by clearing the dis_to bit. i 2 c does not have an idle condition. 5. i 2 c devices do not support the alert response addre ss functionality (which is optional for smbus). 6. i 2 c devices support block read and write differently. i 2 c protocol allows for unlimited number of bytes to be sent in either direction. the smbus protocol requires that an additional data byte indicating number of bytes to read / write is transmitted. the ucs1002 supports i 2 c formatting only. 4.2.3 smbus protocols the ucs1002 is smbus 2.0 compatible and supports write byte, read byte, send byte, and receive byte as valid protocols as shown below. all of the below protocols use the convention in ta b l e 4 . 3 . table 4.3 protocol format data sent to device data sent to the host data sent data sent programmable usb port power controller with charger emulation datasheet smsc ucs1002 31 revision 1.4 (07-16-13) datasheet 4.2.3.1 smbus write byte the write byte is used to write one byte of data to a specific register as shown in table 4.4 . 4.2.3.2 smbus read byte the read byte protocol is used to read one byte of data from the registers as shown in table 4.5 . 4.2.3.3 smbus send byte the send byte protocol is used to set the internal address register pointer to the correct address location. no data is transferred during the send byte protocol as shown in ta b l e 4 . 6 . 4.2.3.4 smbus receive byte the receive byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g., set via send byte). this is used for consecutive reads of the same register as shown in ta b l e 4 . 7 . 4.2.4 i 2 c protocols the ucs1002 supports i 2 c block read and block write. the protocols listed below use the convention in ta b l e 4 . 3 . table 4.4 write byte protocol start client address wr ack register address ack register data ack stop 1 ->0 yyyy_yyy 0 0 xxh 0 xxh 0 0 -> 1 table 4.5 read byte protocol start client address wr ack register address ack start client address rd ack register data nack stop 1->0 yyyy_yyy 0 0 xxh 0 1 ->0 yyyy_yyy 1 0 xxh 1 0 -> 1 table 4.6 send byte protocol start client address wr ack register address ack stop 1 -> 0 yyyy_yyy 0 0 xxh 0 0 -> 1 table 4.7 receive byte protocol start client address rd ack register data nack stop 1 -> 0 yyyy_yyy 1 0 xxh 1 0 -> 1 programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 32 smsc ucs1002 datasheet 4.2.4.1 block write the block write is used to write multiple data byte s to a group of contiguous registers as shown in table 4.8 . application note: when using the block write protocol, the in ternal address pointer will be automatically incremented after every data byte is received. it will wrap from ffh to 00h. 4.2.4.2 block read the block read is used to read multiple data by tes from a group of contig uous registers as shown in table 4.9 . application note: when using the block read protocol, the internal address pointer will be automatically incremented after every data byte is received. it will wrap from ffh to 00h. 4.3 stand-alone operating mode stand-alone mode allows the ucs1002 to operate without active smbus / i 2 c communications. stand- alone mode can be enabled by connecting a pull-down resistor greater or equal to 47 k on the comm_sel / ilim pin as shown in table 4.1, "ucs1002 communication mode and ilim selection" . when the device is configured to op erate in stand-alone mode, the f ault handling and attach detection controls are determined via the latch and s0 pins as shown in table 4.10 . application note: if it is necessary to connect the s0 or lat ch pins to vdd via a pull-up resistor, the pull-up resistor value should be 100 k in order to guarantee v ih specification. likewise, if it is necessary to connect the s0 or latch pins to gnd via a pull-down resistor, the pull-down resistor value should be 100 k in order to guarantee v il specification. table 4.8 block write protocol start client address wr ack register address ack register data ack 1 ->0 yyyy_yyy 0 0 xxh 0 xxh 0 register data ack register data ack . . . register data ack stop xxh 0 xxh 0 . . . xxh 0 0 -> 1 table 4.9 block read protocol start client address wr ack register address ack start client address rd ack register data 1->0 yyyy_yyy 00 xxh 01 ->0 yyyy_yyy 1 0 xxh ack register data ack register data ack register data ack . . . register data nack stop 0 xxh 0 xxh 0 xxh 0 . . . xxh 1 0 -> 1 programmable usb port power controller with charger emulation datasheet smsc ucs1002 33 revision 1.4 (07-16-13) datasheet in the stand-alone operating mode, communications from and to the ucs1002 are limited to the pwr_en, em_en, m2, m1, alert#, and a_det# pins. table 4.10 stand-alone fault and attach detection selection latch pin s0 pin command low low no attach detection. auto-recovery upon error detection. low high attach detection in the detect power state. auto-recovery upon error detection. high low no attach detection. error states ar e latched and require host to change pwr_en control to recover from error state. high high attach detection in the detect power state. error states are latched and require host to change pwr_en control to recover from error state. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 34 smsc ucs1002 datasheet chapter 5 general description the ucs1002 provides a single usb port power switch for precise control of up to 2.5 amperes continuous current with over-cur rent limit (ocl), dynamic therma l management, latch or auto-recovery fault handling, selectable active low or high enable, under- and over-voltage lockout, and back-voltage protection. split supply support for vbus and vdd is an op tion for low power in system standby states. in addition to power switching and current limitin g, the ucs1002 provides automatic and configurable charger emulation profiles to charge a wide variet y of portable devices, including usb-if bc1.2 (cdp or dcp modes), yd/t-1591 (2009), most apple and rim portable devices, and many others. the ucs1002 also provides current monitoring to allow intelligent management of system power and charge rationing for controlled delivery of current r egardless of the host power state. this is especially important for battery operated applic ations that want to provide power and do not want to excessively drain the battery, or that require power a llocation depending on application activities. figure 5.1 shows a ucs1002 full-featured system confi guration in which the ucs1002 provides a port power switch and low power attach detection with wake-up signaling (wake on usb). the current limit is established at power-up. it can be lowered if required after power-up via the smbus / i 2 c. this configuration also provides configurable usb data line charger emulation, programmable current limiting (as determined by the accepted charger emul ation profile), active current monitoring, and port charge rationing. figure 5.1 ucs1002 full-featured system configuration (smbus control) ucs1002 alert# 3 v ? 5.5 v device dpout dmout 5 v vbus1 vbus2 vs1 vs2 a_det# 5 v host cbus usb host 3 v ? 5.5 v ec cin vdd dpin dmin vdd em_en m1 m2 pwr_en smdata smclk sel comm_sel / ilim gnd vdd programmable usb port power controller with charger emulation datasheet smsc ucs1002 35 revision 1.4 (07-16-13) datasheet figure 5.2 shows a system conf iguration in which t he ucs1002 provi des a usb data switch, port power switch, low power attach detection, and port able device attach / removal detection signaling. this configuration does not include configurable data line charger emulation, programmable current limiting, or current monitoring and rationing. . figure 5.3 shows a system configuration in which the ucs1002 provides a port power switch, low power attach detection, and portable device attachment detected signaling. this configuration is useful for applications that already provide usb bc1. 2 and/or legacy data line handshaking on the usb data lines, but still require port power switching and current limiting. figure 5.2 ucs1002 system configuration (cha rger emulation, no smbus, with usb host) ucs1002 latch alert# pwr_en 3 v ? 5.5 v gnd device dpin dmin dpout dmout vdd 5 v vbus1 vbus2 vs1 vs2 comm_sel / ilim 3 v ? 5.5 v auto-recovery upon fault latch upon fault em_en m1 m2 sel a_det# 5 v host cbus usb host s0 disable detect state enable detect state cin vdd > 47k programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 36 smsc ucs1002 datasheet . figure 5.4 shows a system configuration in which the ucs1002 provides a port power switch, low power attach detection, charger emulation (with no usb host), and portable device attachment detected signaling. this configuration is useful for wall adapter type applications. figure 5.3 ucs1002 system configuration (no smbus, no charger emulation) ucs1002 latch alert# pwr_en 3 v ? 5.5 v gnd device dpin dmin dpout dmout vdd 5 v vbus1 vbus2 vs1 vs2 comm_sel / ilim 3 v ? 5.5 v auto-recovery upon fault latch upon fault em_en m1 m2 sel a_det# 5 v host cbus usb host (dp, dm) s0 disable detect state enable detect state cin vdd programmable usb port power controller with charger emulation datasheet smsc ucs1002 37 revision 1.4 (07-16-13) datasheet . ucs1002 references design is available; contact your smsc representative. figure 5.4 ucs1002 system configuration (no sm bus, no usb host, with charger emulation) ucs1002 latch alert# pwr_en 3 v ? 5.5 v gnd device dpin dmin dpout dmout vdd 5 v vbus1 vbus2 vs1 vs2 comm_sel / ilim 3 v ? 5.5 v auto-recovery upon fault latch upon fault em_en m1 m2 sel a_det# 5 v cbus s0 disable detect state enable detect state cin vdd 15 k 15 k programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 38 smsc ucs1002 datasheet 5.1 ucs1002 power states the ucs1002 has the following power states. ? off - this power state is entered when t he voltage at the vdd pin voltage is < v dd_th . in this state the device is considered ?off?. the ucs1002 will not retain its digital states and register contents nor respond to smbus / i 2 c communications. the port power switch, bypass switch, and the high- speed data switches will be off. see section 5.1.1, "off state operation" . ? sleep - this is the lowest power state available. whil e in this state, the ucs1002 will retain digital functionality, respond to changes in emulatio n controls, and wake to respond to smbus / i 2 c communications. the high-speed switch an d all other functionalit y will be disabled. see section 5.1.2, "sleep state operation" . ? detect - this is a lower current power state. in this state, the device is actively looking for a portable device to be attached. the high-speed switch is disabled by default. while in this state, the ucs1002 will retain the configuration and charge rationing data, but it will not monitor the bus current. smbus / i 2 c communications will be fully functional. see section 5.1.3, "detect state operation" . ? error - this power state is entered when a fault condition exists. see section 5.1.5, "error state operation" . ? active - this power state provides full functionality. while in this state, operations include activation of the port power switch, usb data line handshaki ng / charger emulation, current limiting, and charge rationing. see section 5.1.4, "act ive state operation" . programmable usb port power controller with charger emulation datasheet smsc ucs1002 39 revision 1.4 (07-16-13) datasheet table 5.1 shows the settings for the various power states, except off and error. if vdd < v dd_th , the ucs1002 is in the off state. to determine the mode of operation in the active state, see ta b l e 9 . 1 , "active mode selection" . for more information about configuring the ucs1002 to create single or dual mode charger solutions, see smsc application not e 24.20?using the ucs100x as a single or dual mode charger.? application note: using configurations not listed in table 5.1 is not recommended and may produce undesirable results. note 5.1 in order to transition from active state da ta pass-through mode into sleep with these settings, change the m1, m2, and em_en pins before changing the pwr_en pin. see section 9.4, "data pass-through (no charger emulation)" . note 5.2 if s0=?0? and a portable device is not attached in dce cycle mode, the ucs1002 will be cycling through charger emul ation profiles (by default) . there is no guarantee which charger emulation profile will be applied first when a portable device attaches. 5.1.1 off state operation the device will be in the off state if vdd is less than v dd_th . when the ucs1002 is in the off state, it will do nothing, and all circuitry will be disabled. di gital register values are not stored and the device will not respond to smbus commands. table 5.1 power states control settings power state vs pwr_en s0 m1, m2, em_en portable device attached behavior sleep x disabled 0 not set to data pass- through. see note 5.1 . x all switches disabled. vbus will be near ground potential. the ucs1002 wakes to respond to smbus communications. x enabled 0 all = 0b x detect (see chapter 8, detect state ) x disabled 1 x x high-speed switch disabled (by default). port power switch disabled. host-controlled transition to active state (see section 5.1.3.2, "host- controlled transition from detect to active" ). < v s_uvlo enabled 1 all <> 0b x > v s_uvlo enabled 1 all <> 0b no high-speed switch disabled(by default). automati c transition to active state when conditions met (see section 5.1.3.1, "automatic transition from detect to active" ). active (see chapter 9, active state ) > v s_uvlo enabled 0 all <> 0b x high-speed switch enabled / disabled based on mode. port power switch is on at all times. attach and removal detection disabled. see note 5.2 . > v s_uvlo enabled 1 all <> 0b yes port power switch is on. removal detection enabled. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 40 smsc ucs1002 datasheet 5.1.2 sleep state operation when the ucs1002 is in the sleep st ate, the device will be in its lowe st power state. the high-speed switch, bypass switch, and the port power switch will be disabled. the attach and removal detection feature will be disabled. vbus will be near ground pot ential. the alert# pin will not be asserted. if asserted prior to entering the sleep state, the alert# pin will be released. the a_det# pin will be released. smbus activity is limited to single byte read or write. the first data byte read from the ucs1002 when it is in the sleep state will wake it; however, the data to be read will return all 0?s and should be considered invalid. this is a ?dummy? read byte meant to wake the ucs1002. subsequent read or write bytes will be accepted normally. after the dummy read, the ucs1002 will be in a higher power state (see figure 5.6 ). after communication has not occurred for t idle_sleep , the ucs will return to sleep. figure 5.5 shows timing diagrams for waking the ucs1002 via external pins. figure 5.6 shows the timing for waking the ucs1002 via smbus. figure 5.5 wake timing via external pins m1 or m2 port power switch closed (active state) t pin_wake wake with m1 or m2 to active state data pass-through mode (pwr_en enabled, s0 = ?0?, em_en = ?0?, vs > v s_uvlo ) s0 bypass switch closed (detect state) t pin_wake wake with s0 (vs > v s_uvlo , m1 & m2 & em_en not all ?0? and not set to data pass-through) programmable usb port power controller with charger emulation datasheet smsc ucs1002 41 revision 1.4 (07-16-13) datasheet 5.1.3 detect state operation when the ucs1002 is in the detect state, the port power switch will be disabled. the high-speed switch is also disabled by default. the vbus output will be connected to the vdd voltage by a secondary bypass switch (see chapter 8, detect state ). there is one non-recommended configuration which places the ucs1002 in the detect state, but v bus will not be discharged and a portable device at tachment will not be detected. for the recommended configurations, see table 5.1, "power states control settings" . ? not recommended: pwr_en is enabled, s0 = ?1?, and m1, m2, and em_en are all ?0?. there are two methods for transitioning from the dete ct state to the active st ate: automatic and host- controlled. 5.1.3.1 automatic transition from detect to active for the detect state, set s0 to ?1?, enable pwr_en, set the em_en, m1, and m2 controls to the desired active mode ( table 9.1, "active mode selection" ), and supply vs > v s_uvlo . when a portable device is attached and an attach detection event o ccurs, the ucs1002 will autom atically transition to the active state and operate according to the selected active mode. 5.1.3.2 host-controlled transition from detect to active for the detect state, set s0 to ?1?, set the em_e n, m1, and m2 controls to the desired active mode ( table 9.1, "active mode selection" ), and configure one of the following: 1) disable pwr_en and supply vs, or 2) enable pwr_en and don?t supply vs. when a portable device is attached and an attach detection event occurs, the host must respond to transition to the active state. depending on the control settings in the detect state, this coul d entail 1) enabling pwr_en or 2) supplying vs above the threshold. application note: if s0 is '1', pwr_en is enabled, and vs is not present, the a_det# pin will cycle if the current draw exceeds the current capacity of the bypass switch. 5.1.3.3 state change from detect to active when conditions cause the ucs1002 to transition from the detect state to the active state, the following occurs: 1. the attach detection feature will be disabled; the removal detection feature remains enabled, unless s0 is changed to ?0?. figure 5.6 wake via smbus read with s0 = ?0? 0101_111 0 a invalid datan p smbus read a 0001_0000 0101_111 0 a valid data n p 0001_0000 s s t idle_sleep sleep sleep dummy read returns invalid data and places device in temporary active state read returns valid data 0101_111 1 a s 0101_111 1 a s a power state temporary active state (not all functionality available) t smb_wake programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 42 smsc ucs1002 datasheet 2. the bypass switch will be turned off. 3. the discharge switch will be turned on for t discharge . 4. the port power switch will be turned on. 5.1.4 active state operation every time that the ucs1002 enters the active st ate and the port power switch is closed, it will enter the mode as instructed by the host controller (see chapter 9, active state ). the ucs1002 cannot be in the active state (and therefore, the port power sw itch cannot be turned on) if any of the following conditions exist: 1. vs < v s_uvlo . 2. pwr_en is disabled. 3. m1, m2, and em_en are all set to '0'. 4. s0 is set to ?1? and an attach detection event has not occurred. programmable usb port power controller with charger emulation datasheet smsc ucs1002 43 revision 1.4 (07-16-13) datasheet 5.1.5 error state operation the ucs1002 will enter the error state from the ac tive state when any of the following events are detected: 1. the maximum allowable internal die temperature (t tsd ) has been exceeded (see section 7.3.1.2 ). 2. an over-current condition has been detected (see section 7.2.1 ). 3. an under-voltage condition on vbus has been detected (see section 5.2.5 ). 4. a back-drive condition has been detected (see section 5.2.3 ). 5. a discharge error has been detected (see section 7.4 ). 6. an over-voltage condition on the vs pins. the ucs1002 will enter the error state from the de tect state when a back-drive condition has been detected or when the maximum allowable internal die temperature has been exceeded. the ucs1002 will enter the error state from the sleep state when a back-drive condition has been detected. when the ucs1002 enters the error state, the por t power switch, the vbus bypass switch, the high- speed switch are turned off, and the alert# pin is a sserted (by default). they will remain off while in this power state. the ucs1002 will leave this stat e as determined by the f ault handling selection (see section 7.6, "fault handling mechanism" ). when using the latch fault handler and the user has re-activated the device by clearing the err bit (see section 10.3, "status registers" ), or toggling the pwr_en cont rol, the ucs1002 will check that all of the error conditions have been removed. if using auto-recovery fault handler, after the t cycle time period, the ucs1002 will check that all of the error conditions have been removed. if all of the error conditions have been removed, the ucs1002 will return to the active state or detect state, as applicable. returning to the active state will cause the ucs1002 to restart the selected mode (see section 9.2, "active mode selection" ). if the device is in the error state and a removal detection event occurs, it will check the error conditions and then return to the power state defined by the pwr_en, m1, m2, em_en, and s0 controls. 5.2 supply voltages 5.2.1 vdd supply voltage the ucs1002 requires 4.5 v to 5.5 v present on the vdd pin for core device functionality. core device functionality consists of maintaining register states, wake-up upon smbus / i 2 c query, and attach detection. 5.2.2 vs source voltage vs can be a separate supply and can be greater than vdd to accommodate high current applications in which current path resistances result in unacceptable voltage drops that may prevent optimal charging of some portable devices. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 44 smsc ucs1002 datasheet 5.2.3 back-voltage detection whenever the following conditions are true, the po rt power switch will be disabled, the vbus bypass switch will be disabled, the high-speed data switch will be disabled, and a back-voltage event will be flagged. this will cause the ucs1002 to enter the error power state (see section 5.1.5, "error state operation" ). 1. the vbus voltage exceeds the vs voltage by v bv_th and the port power switch is closed. the port power switch will be opened immediately. if the condition lasts for longer than t mask , then the ucs1002 will enter the error state. otherwise, the port power switch will be turned on as soon as the condition is removed. 2. the vbus voltage exceeds the vdd voltage by v bv_th and the vbus bypass switch is closed. the bypass switch will be opened immediately. if the condition lasts for longer than t mask , then the ucs1002 will enter the error state. otherwise, the bypass switch will be turned on as soon as the condition is removed. 5.2.4 back-drive current protection if a portable device is attached that is self-pow ered, it may drive the vbus port to its power supply voltage level; however, the ucs1002 is designed such that leakage current from the vbus pins to the vdd or vs pins shall not exceed i bd_1 (if the vdd voltage is zero) or i bd_2 (if the vdd voltage exceeds v dd_th ). 5.2.5 under-voltage lockout on vs the ucs1002 requires a minimum voltage (v s_uvlo ) be present on the vs pin for active power state. 5.2.6 over-voltage det ection and lockout on vs the ucs1002 port power switch will be disabled if the voltage on the vs pin exceeds a voltage (v s_ov ) for longer than the specified time (t mask ). this will cause the device to enter the error state. 5.3 discrete input pins application note: if it is necessary to connect any of the co ntrol pins except the comm_sel / ilim or sel pins via a resistor to vdd or gnd, the resistor value should not exceed 100 k in order to meet the vih and vil specifications. 5.3.1 comm_sel / ilim input the comm_sel / ilim input determines the initial ilim settings and the communications mode, as shown in table 4.1, "ucs1002 communication mode and ilim selection" . 5.3.2 sel input the sel pin selects the polarity of the pwr_en cont rol. in addition, if t he ucs1002 is not configured to operate in stand-alone mode, the sel pin determines the smbus address. see table 4.2, "sel pin decode" . the sel pin state is latched upon device power-up and further changes will have no effect. programmable usb port power controller with charger emulation datasheet smsc ucs1002 45 revision 1.4 (07-16-13) datasheet 5.3.3 m1, m2, and em_en inputs the m1, m2, and em_en input controls determine t he active mode and affect the power state (see table 5.1, "power states control settings" and table 9.1, "active mode selection" ). when these controls are all set to ?0? and pwr_en is enabled, the ucs1002 attach and removal detection feature is disabled. in smbus mode, the m1, m2, and em_e n pin states will be ignored by the ucs1002 if the pin_ignore configuration bit is set (see section 10.4.3 ); otherwise, the m1_set, m2_set, and em_en_set configuration bits (see section 10.4.3 ) are checked along with the pins. 5.3.4 pwr_en input the pwr_en control enables the port power switch to be turned on if conditions are met and affects the power state (see table 5.1, "power states control settings" ). the port power switch cannot be closed if pwr_en is disabled. however, if pw r_en is enabled, the port power switch is not necessarily closed (see section 5.1.4, "active state operation" ). polarity is controlled by the sel pin. in smbus mode, the pwr_en pin state will be ignored by the ucs1002 if the pin_ignore configuration bit is set (see section 10.4.3 ); otherwise, the pwr_en_set configuration bit (see section 10.4.3 ) is checked along with the pin. 5.3.5 latch input the latch input control determines the behav ior of the fault handling mechanism (see section 7.6, "fault handling mechanism" ). when the ucs1002 is configured to operate in stand-alone mode (see section 4.3, "stand-alone operating mode" ), the latch control is available exclusively via the latch pin (see section table 4.10, "stand-alone fault and attach detection selection" ). when the ucs1002 is configured to operate in smbus mode, the latch control is ava ilable exclusively via the latch_set configuration bit (see section 10.4.3, "switch configuration - 17h" ). 5.3.6 s0 input the s0 control enables the attach and removal de tection feature and affe cts the power state (see table 5.1, "power states control settings" ). when s0 is set to ?1?, an attach detection event must occur before the port power switch can be turned on . when s0 is set to ?0?, the attach and removal detection feature is not enabled. when the device is configured to operate in smbus mode, (see section 4.3, "stand-alone operating mode" ), the s0 control is available exclusiv ely via the s0_set configuration bit (see section 10.4.3, "switch configuration - 17h" ). otherwise, the s0 control is ava ilable exclusively via the s0 pin since the smbus protocol will be disabled. 5.4 discrete output pins 5.4.1 alert# and a_det# output pins the alert# pin is an active low open-drain interrupt to the host controller. the alert# pin is asserted (by default - see alert_mask in section 10.4.1, "general configuration - 15h" ) when an error occurs (see section 10.3.2, "inte rrupt status - 10h" ). the alert# pin can also be asserted when the low_cur (portable device is pulling less current and may be finished charging) or treg (thermal regulation temperature exceeded) bits are set and lin ked. as well, when charge rationing is enabled, the alert# pin is asserted by default when the curre nt rationing threshold is reached (as determined by ration_beh[1:0] - see table 7.1, "charge rationing behavior" ). the alert# pin is released when all conditions that may assert the alert# pin (such as an error condition, charge rationing, and treg and low_chg if linked) have been removed or reset as necessary. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 46 smsc ucs1002 datasheet the a_det# pinprovides an active low open-drain ou tput indication that a valid attach detection event has occurred. it will remain asserted until the ucs100 2 is placed into the sleep state or a removal detection event occurs. for wake on usb, the a_ det# pin assertion can be utilized by the system. if the s0 control is ?0? and the ucs1002 is in t he active state, the a_det# pin will be asserted regardless if a portable device is attached or not. if s0 is '1', pwr_en is enabled, and vs is not present, the a_det# pin will cycle if the current draw exceeds the current capacity of the bypass switch. 5.4.2 interrupt blanking the alert# and a_det# pins will not be asserted for a specified time (up to t blank ) after power-up. additionally, an error condition (except for the ther mal shutdown) must be present for longer than a specified time (t mask ) before the alert# pin is asserted. programmable usb port power controller with charger emulation datasheet smsc ucs1002 47 revision 1.4 (07-16-13) datasheet chapter 6 usb high-speed data switch 6.1 usb high-speed data switch the ucs1002 contains a series usb 2.0 compliant high-speed switch between the dpin and dmin pins and between the dpout and dmout pins. this switch is designed for high-speed, low latency functionality to allow usb 2.0 full-speed and high- speed communications with minimal interference. nominally, the switch is closed in the active state, allowing uninterrupted usb communications between the upstream host and the portable device. the switch is opened when: 1. the ucs1002 is actively emulating using any of the charger emulation profiles except cdp (by default - see section 10.4.5, "high-speed switch configuration - 25h" ). 2. the ucs1002 is operating as a dedicated charge r unless the hsw_dce configuration bit is set (see section 10.4.5 ). 3. the ucs1002 is in the detect state (by default) or in the sleep state. application note: if the vdd voltage is less than v dd_th , the high-speed data switch will be disabled and opened. 6.1.1 usb-if high-speed compliance the usb data switch will not significantly degrade the signal integrity through the device dp / dm pins with usb high-speed communications. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 48 smsc ucs1002 datasheet chapter 7 usb port power switch 7.1 usb port power switch to assure compliance to various charging specifications, the ucs1002 contains a usb port power switch that supports two current limiting modes: tr ip and constant current (variable slope). the current limit (ilim) is pin selectable (and may be updated via the register set). the switch also includes soft start circuitry and a separate short circuit current limit. the port power switch is on in the active state (except when vbus is discharging). 7.2 current limiting 7.2.1 current limit setting the ucs1002 hardware set current limit, ilim, can be one of eight values (see table 4.1, "ucs1002 communication mode and ilim selection" ). this resistor value is read once upon ucs1002 power-up. the current limit can be changed via the smbus / i 2 c after power-up; howe ver, the programmed current limit cannot exceed the hardware set current limit. at power-up, the communication mode (stand-alone or smbus / i 2 c) and hardware current limit (ilim) are determined via the pull-down resistor (or pull- up resistor if connected to vdd) on the comm_sel / ilim pin, as shown in table 4.1 . 7.2.2 short circuit out put current limiting short circuit current limiting occurs when the outp ut current is above the selectable current limit (i limx ). this event will be detected and the current will immediately be limited (within t short_lim time). if the condition remains, the port power switch will flag an error condition and enter the error state (see section 5.1.5, "error state operation" ). 7.2.3 soft start when the pwr_en control changes states to enable the port power switch, or an attach detection event occurs in the detect power state and t he pwr_en control is already enabled, the ucs1002 invokes a soft start routine for t he duration of the vbus rise time (t r_bus ). this soft start routine will limit current flow from vs into vbus while it is acti ve. this circuitry will prevent current spikes due to a step in the portable device current draw. in the case when a portable device is attached while the pwr_en pin is already enabled, if the bus current exceeds ilim, the ucs1002 current li miter will respond within a specified time (t short_lim ) and will operate normally at this point. the c bus capacitor will deliver the extra current, if any, as required by the load change. 7.2.4 current limiting modes the ucs1002 current limiting has two modes: trip and constant current (varia ble slope). either mode functions at all times when the port power switch is closed. the current limiting mode used depends on the active state mode (see section 9.9, "current limit mode associations" ). when operating in the detect power state (see section 5.1.3 ), the current capacity at vbus is limited to i bus_byp as described in section 8.2, "vbus bypass switch" . programmable usb port power controller with charger emulation datasheet smsc ucs1002 49 revision 1.4 (07-16-13) datasheet 7.2.4.1 trip mode when using trip current limiting, the ucs1002 usb port power switch functions as a low resistance switch and rapidly turns off if the current limit is exceeded. while operating using trip current limiting, the vbus output voltage will be held relatively constant (equal to the vs voltage minus the r on * ibus current) for all current values up to the ilim. if the current drawn by a portable device exceeds ilim, the following occurs: 1. the port power switch will be turned off (trip action). 2. the ucs1002 will enter the error st ate and assert the alert# pin. 3. the fault handling circuitry will then determine subsequent actions. trip current limiting is used by default when the ucs1002 is in data pass-through and dedicated charger emulation cycle (except when the bc1.2 dcp charger emulation profile is accepted), and when there?s no handshake. application note: to avoid cycling in trip mode, set ilim higher than the highest expected portable device current draw. figure 7.1 shows operation of current limits in trip mode with the shaded area representing the usb 2.0 specified vbus range. dashed lines indicate the port power switch output will go to zero (e.g., trip) when ilim is exceeded. note that operation at all possible values of ilim are shown in figure 7.1 for illustrative purposes only; in actual operat ion only one ilim can be active at any time. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 50 smsc ucs1002 datasheet 7.2.4.2 constant current limiting (variable slope) constant current limiting is used when a port able device handshakes using the bc1.2 dcp charger emulation profile and the current drawn is greater than ilim (and ilim < 1.5 a). it?s also used in bc1.2 cdp mode and during the dce cycle when a charger emulation profile is being applied and the emulation timeout is active. in cc mode, the port power switch allows the atta ched portable device to reduce vbus output voltage to less than the input vs voltage while maintaining current delivery. the v/i slope depends on the user set ilim value. this slope is held constant for a given ilim value. figure 7.1 trip current limiting operation 5 4 3 2 1 0.5 1.0 1.5 2.0 2.5 5.25 4.75 ibus (amps) vbus (volts) operating current 0 0 0.9 1.2 1.2 1.0 0.9 0.5 1.5 2.5 1.8 2.0 = ilim?s 1.8 power switch voltage and current output go to zero when ilim is exceeded trip action (ilim = 0.5 a) trip action (ilim = 2.5 a) ilim (amps) programmable usb port power controller with charger emulation datasheet smsc ucs1002 51 revision 1.4 (07-16-13) datasheet figure 7.2 shows operation of current limits while usin g cc mode. unlike trip mode, once ibus current exceeds ilim, operation continues at a reduced volt age and increased current. note that the shaded area representing the usb 2.0 specified vbus range is now restricted to an upper current limit of i bus_r2min . note that the ucs1002 will heat up alon g each load line as voltage decreases. if the internal temperature exceeds the t reg or t tsd thresholds, the port power switch will open. also note that when the vbus voltage is brought low enough (below v bus_min ), the port power switch will open. 7.3 thermal management and voltage protection 7.3.1 thermal management the ucs1002 utilizes two-stage internal thermal management. the first is named dynamic thermal management and the second is a fixed thermal shutdown. figure 7.2 constant current limiting (variable slope) operation 5 4 3 2 1 0.5 1.0 1.5 2.0 2.5 5.25 4.75 0 0 0.9 1.2 1.2 1.0 0.9 0.5 1.5 ibus_r2min 1.8 1.8 2.0 2.5 ibus (amps) vbus (volts) ilim (amps) = ilim?s constant resistance i bus operation line 1 (ilim = 0.5 a) constant resistance i bus operation line 5 (ilim = 1.5 a*) cc mode - power switch current increases as voltage decreases when ilim is exceeded following constant resistance lines *1.5 a limit reduced by -3.5% internally programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 52 smsc ucs1002 datasheet 7.3.1.1 dynamic thermal management for the first stage (active in both current limiting modes), referred to as dynamic thermal management, the ucs1002 automatically adjusts port power swit ch limits and modes to lower power dissipation when the thermal regulation temperature value is approached, as described below. if the internal temperature exceeds the t reg value, the port power switch is opened, the current limit (ilim) will be lowered by one step and a timer is started (t dc_temp ). when this timer expires, the port power switch is closed and the internal temperat ure will be checked again. if it remains above the t reg threshold, the ucs1002 will repeat this cycle (open po rt power switch and reduce the ilim setting by one step) until ilim reaches its minimum value. application note: if the temperature exceeds the treg threshold while operating in the dce cycle mode after a charger emulation profile has been accepted, the profile will be removed. the ucs1002 will not restart the dce cycle until one of the control inputs changes states to restart emulation. application note: the ucs1002 will not actively discharge vbus as a result of the temperature exceeding treg; however, any load current provided by a portable device or other load will cause vbus to be discharged when the port power switch is opened, possibly resulting in an attached portable device resetting. if the ucs1002 is operating using constant current limit ing (variable slope) and the ilim setting has been reduced to its minimum set point and the temperature is still above t reg , the ucs1002 will switch to operating using trip current limit ing. this will be done by reducing the i bus_r2min setting to 100 ma and restoring the ilim setting to the value immediately below the programmed setting (e.g., if the programmed ilim is 1.8 a, the value will be set to 1.5 a). if the temperature continues to remain above t reg , the ucs1002 will continue this cycle (open the port power switch and reduce the ilim setting by one step). if the ucs1002 internal temperature drops below t reg - t reg_hyst , the ucs1002 will take action based on the following: 1. if the current limit mode changed from cc mode to trip mode, then a timer is started. when this timer expires, the ucs1002 will reset the port power switch operation to its original configuration allowing it to operate using constant current limiting (variable slope). 2. if the current limit mode did not change from cc mode to trip mode, or was already operating in trip mode, the ucs1002 will reset the port power swit ch operation to its original configuration. if the ucs1002 is operating using trip current limiting and the ilim setting has been reduced to its minimum set point and the temperature is above t reg , the port power switch will be closed and the current limit will be held at its minimum setting until the temperature drops below t reg - t reg_hyst . 7.3.1.2 thermal shutdown the second stage thermal management consists of a hardware implemented thermal shutdown corresponding to the ma ximum allowable internal die temperature (t tsd ). if the internal temperature exceeds this value, the port power switch will immediately be turned off until the temperature is below t tsd - t tsd_hyst . programmable usb port power controller with charger emulation datasheet smsc ucs1002 53 revision 1.4 (07-16-13) datasheet 7.4 vbus discharge the ucs1002 will discharge v bus through an internal 100 resistor when at least one of the following conditions occurs: ? the pwr_en control is disabled (triggered on the inactive edge of the pwr_en control). ? a portable device removal detection event is flagged. ? the vs voltage drops below a specified threshold (v s_uvlo ) that causes the port power switch to be disabled. ? when commanded into the sleep power state via the em_en, m1, and m2 controls. ? before each charger emulation profile is applied. ? upon recovery from the error state. ? when commanded via the smbus (see section 10.4, "configuration registers" ) in the active state. ? any time that the port power switch is activa ted after the vbus bypass switch has been on (i.e., whenever vbus voltage transitions from being driven from vdd to being driven from vs, such as going from detect to active power state). ? any time that the vbus bypass switch is activat ed after the port power switch has been on (i.e., going from active to detect power state). when the vbus discharge circuitry is activated, at the end of the t discharge time, the ucs1002 will confirm that vbus was discharged. if the vbus voltage is not below the v test level, a discharge error will be flagged (by setting the discharge_err status bit) and the ucs1002 will enter the error state. 7.5 battery full delivery of bus current to a portable device can be rationed by the ucs1002. when this functionality is enabled, the host system mu st provide the ucs1002 with an accumulated charge maximum limit (in milliampere-hours). the charge rationing functional ity works only in the active power state. it continuously monitors the current delivered as well as the time elapsed since the mode was activated (or since the data was updated). this information is compiled to generate a charge-rationing number that is checked against the host limit. once the programmed current-rationing limit has been reached, the ucs1002 will take action as determined by the ration_beh bits as described in table 7.1 . note that this does not cause the device to enter the error state. once the charge rationing circuitry has reached the programmed threshold, the ucs1002 will maintain the desired behavior until charge rationing is reset. once charge rationing has been reset or disabled, the ucs1002 will recover as shown in ta b l e 7 . 2 . programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 54 smsc ucs1002 datasheet table 7.1 charge rationing behavior ration_beh [1:0] behavior actions taken notes 10 0 0 report alert# pin asserted. 0 1 report and disconnect (default) 1. alert# pin asserted. 2. charger emulation profile removed. 3. port power switch disconnected. the hsw will not be affected. all bus monitoring is still active. changing the m1, m2, em_en, s0, and pwr_en controls will cause the device to change power states as defined by the pin combinations; however, the port power switch will remain off until the rationing circuitry is reset. furthermore, the bypass switch will not be turned on if enabled via the s0 control. 1 0 disconnect and go to sleep 1. port power switch disconnected. 2. charger emulation profile removed. 3. device will enter the sleep state. the hsw will be disabled. all vbus and vs monitoring will be stopped. changing the m1, m2, em_en, s0, and pwr_en controls will have no effect on the power state until the rationing circuitry is reset. 1 1 ignore take no further action. table 7.2 charge rationing reset behavior behavior reset actions report 1. reset the total accumulated charge registers. 2. clear the ration status bit. 3. release the alert# pin. report and disconnect 1. reset the total accumulated charge registers. 2. clear the ration status bit. 3. release the alert# pin. 4. check the m1, m2, em_en, s0, and pwr_en controls and enter the indicated power state if the controls changed (see note 7.1 ). disconnect and go to sleep 1. reset the total accumulated charge registers. 2. clear the ration status bit. 3. check the m1, m2, em_en, s0, and pwr_en controls and enter the indicated power state if the controls changed (see note 7.1 ). ignore 1. reset the total accumulated charge registers. 2. clear the ration status bit. programmable usb port power controller with charger emulation datasheet smsc ucs1002 55 revision 1.4 (07-16-13) datasheet note 7.1 any time the charge ra tioning circuitry checks the pin conditions when ch anging rationing behavior or resetting charge rationing, if the external pin conditions have changed, then charger emulation will be restarted (provided em ulation is enabled via the pin states). if the pin conditions have not c hanged, the ucs1002 return to the previous power state as if the rationing threshold had not been reached (e.g., it will not discharge vbus or restart emulation). 7.5.1 charge rationing interactions when charge rationing is active, regardless of the specified behavior, the ucs1002 will function normally until the charge rationing threshold is reach ed. note that charge rationing is only active when the ucs1002 is in the active state, and it doe s not automatically reset when a removal or attach detection event occurs. charger emulation will start over if a removal detection event and attach detection event occur while charge rationing is active and the charge rationing threshold has not been reached. this allows charging of sequential portable devices while charge is being rationed, which means that the accumulated power given to several portable devices will still be held to the stated rationing limit. changing the charge rationing behavior will have no effect on the charge rationing data registers. if the behavior is changed prior to reaching the charge rationing threshold, this change will occur and be transparent to the user. when the charge rationing th reshold is reached, the ucs1002 will take action as shown in ta b l e 7 . 1 . if the behavior is changed after the charge rationing threshold has been reached, the ucs1002 will immediately adopt t he newly programmed behavior, clearing the alert# pin and restoring switch operation respectively (see table 7.3 ). table 7.3 effects of changing rationing behavior after threshold reached previous behavior new behavior actions taken ignore report assert alert# pin. report and disconnect 1. assert alert# pin. 2. remove charger emulation profile. 3. open port power switch. see the ?report and disconnect? entry in ta b l e 7 . 1 . disconnect and go to sleep 1. remove charger emulation profile. 2. open port power switch. 3. enter the sleep state. see the ?disconnect and go to sleep? entry in ta b l e 7 . 1 . report ignore release alert# pin. report and disconnect open port power switch. see the ?report and disconnect? entry in ta b l e 7 . 1 . disconnect and go to sleep 1. release the alert# pin. 2. remove charger emulation profile. 3. open the port power switch. 4. enter the sleep state. see the ?disconnect and go to sleep? entry in ta b l e 7 . 1 . programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 56 smsc ucs1002 datasheet if the ration_en control is set to ?0? prior to reac hing the charge rationing threshold, rationing will be disabled and the total accumulated charge register s will be cleared. if the ration_en control is set to ?0? after the charge rationing threshold has been reached, the following will be done: 1. ration status bit will be cleared. 2. the alert# pin will be released if asserted by t he rationing circuitry and no other conditions are present. 3. the m1, m2, em_en, s0, and pwr_en controls are checked to determine the power state. see note 7.1 . application note: if the rationing behavior was set to ?report and disconnect? when the charge rationing threshold was reached and then the ration_en bi t is cleared, the portable device may start charging suboptimally because the charger emulation profile has been removed. toggle the pwr_en control to restart charger emulation. setting the ration_rst control to ?1? will automati cally reset the total accumulated charge registers to 00_00h. if this is done prior to reaching the charge rationing threshold, the data will continue to be accumulated restarting from 00_00h. if this is done after the charge rationing threshold is reached, the ucs1002 will take action as shown in ta b l e 7 . 2 . 7.6 fault handling mechanism the ucs1002 has two modes for handling faults: latch (latch-upon-fault) or auto-recovery (automatically attempt to restore the active power st ate after a fault occurs). if the smbus is actively utilized, auto-recovery fault handl ing is the default error handler as determined by the latch_set bit (see section 10.4.3, "switch configuration - 17h" ). otherwise, the fault handling mechanism used depends on the state of the latch pin. faults in clude over-current, over-voltage (on vs), under- report and disconnect ignore 1. release the alert# pin. 2. check the m1, m2, em_en, s0, and pwr_en controls and enter the indicated power state if the controls changed (see note 7.1 ). report check the m1, m2, em_en, s0, and pwr_en controls and enter the indicated power state if the controls changed (see note 7.1 ). disconnect and go to sleep 1. release the alert# pin. 2. enter the sleep state. see the ?disconnect and go to sleep? entry in ta b l e 7 . 1 . disconnect and go to sleep ignore check the m1, m2, em_en, s0, and pwr_en controls and enter the indicated power state if the controls changed (see note 7.1 ). report 1. assert the alert# pin. 2. check the m1, m2, em_en, s0, and pwr_en controls and enter the indicated power state if the controls changed (see note 7.1 ). report and disconnect 1. assert the alert# pin. 2. check the m1, m2, em_en, s0, and pwr_en controls to determine the power state then enter that state e xcept that the port power switch and bypass switch will not be closed (see note 7.1 ). table 7.3 effects of changing rationing behavior after threshold reached (continued) previous behavior new behavior actions taken programmable usb port power controller with charger emulation datasheet smsc ucs1002 57 revision 1.4 (07-16-13) datasheet voltage (on vbus), back-voltage (vbus to vs or vbus to vdd), discharge error, and maximum allowable internal die temperature (t tsd ) exceeded (see section 5.1.5, "error state operation" ). 7.6.1 auto-recovery fault handling when the latch control is low, auto-recovery fault handling is used. when an error condition is detected, the ucs1002 will immediately enter the error state and assert the alert# pin (see section 5.1.5 ). independently from the hos t controller, the ucs1002 will wait a preset time (t cycle ), check error conditions (t tst ), and restore active operation if the error condition(s) no longer exist. if all other conditions that may cause the alert# pin to be asserted have been removed, the alert# pin will be released. 7.6.2 latched fault handling when the latch control is high, latch fault handling is used. when an error co ndition is detected, the ucs1002 will enter the error power state and assert the alert# pin. upon command from the host controller (by toggling the pwr_en control from ena bled to disabled or by clearing the err bit via smbus), the ucs1002 will check error conditions once and restore active operation if error conditions no longer exist. if an error condition still exists, the host controller is required to issue the command again to check error conditions. figure 7.3 error recovery timing (short circuit example) t rst vbus ibus short applied. i tst t discharg e i tst v test short detected. vbus discharged. enter error state. check short condition. short still present. return to error state. wait t cycle . wait t cycle . check short condition. short removed. return to normal operation. t cycle t cycle t rst programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 58 smsc ucs1002 datasheet chapter 8 detect state 8.1 device attach / removal detection the ucs1002 can detect the attachment and remo val of a portable device on the usb port. attach and removal detection does not perform any charger emulation or qualification of the device. the high-speed switch is ?off? (by defaul t) during the detect power state. 8.2 vbus bypass switch the ucs1002 contains circuitry to provide vbus current as shown in figure 8.1 . in the detect state, vdd is the voltage source; in the active state, vs is the voltage source. the bypass switch and the port power switch are never both on at the same time. while the vbus bypass switch is ac tive, the current available to a portable device will be limited to i bus_byp , and the attach detection feature is active. 8.3 attach detection the attach detection feature is only active in the detect power state. when active, this feature constantly monitors the current load on the vbus pin. if the current drawn by a portable device is greater than i det_qual for longer than t det_qual , an attach detection event occurs. this will cause the a_det# pin to assert low and the adet_pin and att status bits to be set. until the port power switch is enabled, the current av ailable to a portable device will be limited to that used to detect device attachment (i det_qual ). once an attach detection event occurs, the ucs1002 will wait for the pwr_en control to be enabled (if not already). when pwr_en is enabled and vs is above the threshold, the ucs1002 will activate the usb port power switch and operate in the selected active mode (see chapter 9, active state ). 8.4 removal detection the removal detection feature will be active in th e active and detect power states if s0 = 1. this feature monitors the current load on the vbus pin. if this load drops to less than i rem_qual_det for longer than t rem_qual , a removal detection event is flagged. when a removal detection event is flagged, the following will be done: 1. disable the port power switch and the bypass switch. figure 8.1 detect st ate vbus biasing port power switch vdd v s v s v bus v bus bypass switch programmable usb port power controller with charger emulation datasheet smsc ucs1002 59 revision 1.4 (07-16-13) datasheet 2. de-assert the a_det# pinucs1002 a nd set the rem status register bit. 3. enable an internal discharging device that will discharge the vbus line within t discharge . 4. once the vbus pin has been discharged, the device will return to the detect state regardless of the pwr_en control state. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 60 smsc ucs1002 datasheet chapter 9 active state 9.1 active state overview the ucs1002 has the following modes of operation in the active state: data pass-through, bc1.2 dcp, bc1.2 sdp, bc1.2 cdp, and dedicated charger emulation cycle. the current limiting mode depends on the active mode behavior (see table 9.2, "current limit mode options" ). 9.2 active mode selection the active mode selection is controlled by three controls: em_en, m1, and m2, as shown in ta b l e 9 . 1 . note 9.1 bc1.2 sdp behaves the same as the data pass-through mode with the exception that it is preceded by a vbus discharge when the mode is entered per the bc1.2 specification. 9.3 bc1.2 detection renegotiation the bc1.2 specification allows a charger to act as an sdp, cdp, or dcp and to change between these roles. to force an attached portable device to re peat the charging detection procedure, vbus must be cycled. in compliance with this sp ecification, the ucs1 002 automatically cycles vbus when switching between the bc1.2 sdp, bc1. 2 dcp, and bc1.2 cdp modes. 9.4 data pass-through (n o charger emulation) when commanded to data pass-through mode, ucs1002 will close its usb high-speed data switch to allow usb communications between a portable dev ice and host controller and will operate using trip current limiting. no charger emul ation profiles are applied in this mode. data pass-through mode will persist until commanded otherwise by the m1, m2, and em_en controls. application note: if it is desired that the data pass-throu gh mode operates as a traditional / standard port power switch, the s0 control should be set to ?0?. when entering this mode, there is no automatic vbus discharge. table 9.1 active mode selection # m1 m2 em_en active mode 1 0 0 1 dedicated charger emulation cycle 2 0 1 0 data pass-through 3 0 1 1 bc1.2 dcp 4 1 0 0 bc1.2 sdp - see note 9.1 5 1 0 1 dedicated charger emulation cycle 6 1 1 0 data pass-through 7 1 1 1 bc1.2 cdp programmable usb port power controller with charger emulation datasheet smsc ucs1002 61 revision 1.4 (07-16-13) datasheet application note: when the m1, m2, and em_en controls are set to ?0?, ?1?, ?0? or to ?1?, ?1?, ?0? respectively, data pass-through mode will persist if the pwr_en control is disabled; however, the ucs1002 will draw more current. to leave data pass-through mode, the pwr_en control must be enabled before the m1, m2, and em_en controls are changed to the desired mode. 9.5 bc1.2 sdp (no charger emulation) when commanded to bc1.2 sdp mode, ucs1002 will discharge vbus, close its usb high-speed data switch to allow usb communications between a portable device and host controller, and will operate using trip current limiting. no charger em ulation profiles are applied in this mode. bc1.2 sdp mode will persist until commanded otherwise by the m1, m2, em_en, and pwr_en controls. application note: if it is desired that the bc1.2 sdp mode oper ates as a traditional / standard port power switch, the s0 control should be set to ?0?. 9.6 bc1.2 cdp when bc1.2 cdp is selected as the active mode, ucs1002 will discharge vbus, close its usb high- speed data switch (by default), and apply the bc1.2 cdp charger emulation profile which performs handshaking per the specification. the combination of the ucs1002 cdp handshake along with a standard usb host comprises a charging downstream port. in bc1.2 cdp mode, there is no emulation timeout. if the handshake is successful, the ucs1002 will operat e using constant current limiting (variable slope). if the handshake is not successful, the ucs1 002 will leave the applied cdp profile in place, leave the high-speed switch closed, enable constant current limiting, an d persist in this condition until commanded otherwise by the m1, m2, em_en, and pwr_en controls. the ucs1002 will respond per the bc1.2 specificat ion to portable device initiated charger renegotiation requests. application note: bc1.2 compliance testing may require the s0 control to be set to ?0? (attach and removal detection feature disabled) while testing is in progress. application note: when the ucs1002 is in bc1.2 cdp mode and the attach and removal detection feature is enabled, if a power thief, such as a usb ligh t or fan, attaches but does not assert dp, a removal event will not occur when the portable device is removed. however, if a standard usb device is subsequently attached, removal detection will again be fully functional. as well, if pwr_en is cycled or m1, m2, and / or em_en change state, a removal event will occur and attach detection will be reactivated. 9.6.1 bc1.2 cdp charger emulation profile the bc1.2 cdp charger emulation profile acts as described below. application note: all cdp handshaking is performed with the high-speed switch closed. 1. vbus voltage is applied. 2. primary detection - when the portable device drives a voltage between 0.4 v and 0.8 v onto the dpout pin, the ucs1002 will drive 0.6 v onto the dmout pin within 20 ms. 3. when the portable device drives the dpout pin back to ?0?, the ucs1002 will then drive the dmout pin back to ?0? within 20 ms. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 62 smsc ucs1002 datasheet 4. optional secondary detection - if the portable devi ce then drives a voltage of 0.6 v (nominal) onto the dmout pin, the ucs1002 will take no other action. this will cause the portable device to observe a ?0? on the dpout pin and know that it is connected to a cdp. 9.7 bc1.2 dcp when bc1.2 dcp is selected as the active mode, ucs1002 will discharge vbus and apply the bc1.2 dcp charger emulation profile per the specification. in bc1.2 dcp mode, the emulation timeout and requirement for portable device current draw are automatically disabled. when the bc1.2 dcp charger emulation profile is applied within the dedicated charger emulation cycle (see section 9.11.1, "bc1.2 dcp charger emulation profile within dce cycle" ), the timeout and current draw requirement are enabled. if the portable device is charging after the dcp charger emulation profile is applied, the ucs1002 will leave in place the resistive short, leave the high-speed switch open, and enable constant current limiting (variable slope). application note: bc1.2 compliance testing may require the s0 control to be set to ?0? (attach and removal detection feature disabled) while testing is in progress. 9.7.1 bc1.2 dcp charger emulation profile the bc1.2 dcp charger emulation profile is described below. 1. vbus voltage is applied. a resistor (r dcp_res ) is connected between the dpout and dmout pins. 2. primary detection - if the portable device driv es 0.6 v (nominal) onto the dpout pin, the ucs1002 will take no other action than to leave the re sistor connected between dpout and dmout. this will cause the portable device to see 0.6 v (nominal) on the dmout pin and know that it is connected to a dcp. 3. optional secondary detection - if the portable dev ice drives 0.6 v (nominal) onto the dmout pin, the ucs1002 will take no other action than to leave the resistor connected between dpout and dmout. this will cause the portable device to see 0.6 v (nominal) on the dpout pin and know that it is connected to a dcp. 9.8 dedicated charger when commanded to dedicated charger emulation cycle mode, the ucs1002 enables an attached portable device to enter its charging mode by applying specific charger emulation profiles in a predefined sequence. using these profiles, the ucs1002 is capable of generating and recognizing several signal levels on the dpout and dmout pins. the preloaded charger emulation profiles include ones compatible with bc1.2 dcp, yd/t-1591 (2009) and most apple and rim portable devices. other levels, sequences, and protoc ols are configurable via the smbus / i 2 c. when a charger emulation profile is applied, a progra mmable timer for the emulation profile is started. when emulation timeout occurs, the ucs1002 chec ks the ibus current against a programmable threshold. if the current is above the threshold, the charger emulation profile is accepted and the associated current limiting mode is applied. no active usb data communication is possible when charging in this mode (by default - see section 10.4.5, "high-speed switch configuration - 25h" ). 9.8.1 emulation reset prior to applying any of the charger emulation pr ofiles, the ucs1002 will perform an emulation reset. this involves the following: programmable usb port power controller with charger emulation datasheet smsc ucs1002 63 revision 1.4 (07-16-13) datasheet 1. the ucs1002 resets the vbus line by disconnecting the port power switch and connecting vbus to ground via an internal 100 resistor for t discharge time. the port power switch will be held open for a time equal to t em_reset at which point the port power switch will be closed and the vbus voltage applied. 2. the dpout and dmout pins will be pulled low using internal 15 k pull-down resistors. application note: to help prevent possible damage to a portable device, the dpout and dmout pins have current limiting in place when the emulation profiles are applied. 9.8.2 emulation cycling in dedicated charger emulation cycle mode, the char ger emulation profiles (if enabled) will be applied in the following order: 1. legacy 1 2. bc1.2 dcp 3. legacy 2 4. legacy 3 5. legacy 4 6. legacy 5 7. legacy 6 8. legacy 7 9. custom (disabled by default). if the cs1_first configuration bit is set, then the custom charger emulation profile will be tested firs t and the order will proceed as given. application note: if s0=?0? and a portable device is not attached in dce cycle mode, the ucs1002 will be cycling through charger emulation profiles (b y default). there is no guarantee which charger emulation profile will be applied first when a portable device attaches. the ucs1002 will apply a charger emulation profile unt il one of the following exit conditions occurs: 1. current greater than i bus_chg is detected flowing out of vbus at the respective emulation timeout time. in this case, the profile is assumed to be accepted and no other profiles will be applied. 2. the respective emulation timeout (t em_timeout ) time is reached without current that exceeds the i bus_chg limit flowing out of vbus (the emul ation timeout is enabled by default, see section 10.4.2, "emulation c onfiguration - 16h" and section 10.13.1, "custom emulation configuration - 40h" ). the profile is assumed to be rejected, a nd the ucs1002 will perform emulation reset and apply the next profile, if there is one. emulation timeouts can be programmed for each charger emulation profile (see section 10.11, "preloaded emulation timeout configuration registers" and section 10.13.1, "custom emulation configuration - 40h" ). 9.8.3 dce cycle retry if none of the charger emulation profiles cause a charge current to be drawn, the ucs1002 will perform emulation reset and cycle through the profiles agai n (if the em_retry bit is set (default - see section 10.4.2, "emulation c onfiguration - 16h" )). the ucs1002 will co ntinue to cycle thro ugh the profiles so as long as charging current is not drawn and the pw r_en control is enabled. if the emulation retry is not enabled, the ucs1002 will flag ?no handshake? and end the dce cycle using trip current limiting. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 64 smsc ucs1002 datasheet 9.9 current limit mode associations the ucs1002 will close the port power switch and use the current limiting mode as shown in ta b l e 9 . 2 . as noted in the last three rows in table 9.2 , under those specific conditions with ilim < 1.5 a, it is the relationship of ilim and i bus_r2min that determines the current limiti ng mode. in these cases, the value of i bus_r2min is determined by cs_r2_imin[2:0] bits 4-2 in the custom current limiting behavior configuration register 51h. 9.10 no handshake in dce cycle mode with emulation retry disabled, a ?no handshake? condit ion is flagged (the no_hs status bit stays set (see section 10.3.4, "profile status 1 - 12h" )) when the end of the dce cycle is reached without a handshake and without drawing current. all signatures / handshaking placed on the dpout and dmout pins are removed. the ucs1002 will operate with the high-speed switch opened or cl osed as determined by the high-speed switch configuration and will use trip or constant current limiting as determined by the i bus_r2min setting (cs_r2_imin[2:0] bits 4-2 in t he custom current limiting behavio r configuration register 51h). table 9.2 current li mit mode options active mode current limit mode (see section 10.14 ) data pass-through trip mode bc1.2 dcp cc mode if ilim < 1.5 a, otherwise, trip mode bc1.2 sdp trip mode bc1.2 cdp cc mode if ilim < 1.5 a, otherwise, trip mode dce cycle during dce cycle when a charger emulation profile is being applied and the emulation timeout is active cc mode if ilim < 1.5 a, otherwise, trip mode bc1.2 dcp charger emulation profile accepted or the emulation timeout is disabled cc mode if ilim < 1.5 a, otherwise, trip mode legacy 2 charger emulation profile accepted or the emulation timeout is disabled cc mode if ilim < 1.5 a, otherwise, trip mode legacy 1 or legacy 3 - legacy 7 charger emulation profile accepted or the emulation timeout is disabled trip mode if i bus_r2min < ilim or ilim > 1.5 a (normal operation), otherwise, cc mode (see section 10.14.2 ) custom charger emulation profile accepted or the emulation timeout is disabled trip mode if i bus_r2min < ilim or ilim > 1.5 a (normal operation), otherwise, cc mode (see section 10.14.2 ) no handshake (dce cycle with emulation retry not enabled) trip mode if i bus_r2min < ilim or ilim > 1.5 a (normal operation), otherwise, cc mode (see section 10.14.2 ) programmable usb port power controller with charger emulation datasheet smsc ucs1002 65 revision 1.4 (07-16-13) datasheet portable devices that can cause this are generally ones that pull up dpout to some voltage and leave it there, or apply the wrong voltage. 9.11 preloaded charger emulation profiles the following charger emulation profiles are resident to the ucs1002: 1. legacy 1, 3, 4, and 6 - see section 9.11.3 2. legacy 2 - see section 9.11.2 3. legacy 5 - see section 9.11.4 4. legacy 7 - see section 9.11.5 5. bc1.2 cdp - see section 9.6.1 6. bc1.2 dcp - see section 9.7.1 additionally, the user may ?build? a charger emulation profile by determining the voltage and resistance characteristics that are placed on ea ch of the dpout and dmout pins. see section 9.12, "custom charger emulation profile" . 9.11.1 bc1.2 dcp charger emulat ion profile within dce cycle when the bc1.2 dcp charger emulation profile ( section 9.7.1, "bc1.2 dcp charger emulation profile" ) is applied within the dce cycle (dedicated c harger emulation cycle is selected as the active mode), the behavior after the profile is applied is different than active mode bc1.2 dcp (bc1.2 dcp in ta b l e 9 . 1 ) because the t em_timeout timer is enabled (by default) during the dce cycle. during the dce cycle after the dcp charger emulat ion profile, the ucs1002 will perform one of the following: 1. if the portable device is drawing more than i bus_chg current when the t em_timeout timer expires, the ucs1002 will flag that a bc1.2 dcp was detected. the ucs1002 will leave in place the resistive short , leave the high-speed switch open, and then enable constant current limiting (variable slope). 2. if the portable device does not draw more than i bus_chg current when the t em_timeout timer expires, the ucs1002 will stop applying the dcp ch arger emulation profile and proceed to the next charger emulation profil e in the dce cycle. 9.11.2 legacy 2 charger emulation profile the legacy 2 charger emulation profile does the following: 1. the ucs1002 will connect a resistor (r dcp_res ) between dpout and dmout. 2. vbus is applied. 3. if the portable device draws more than i bus_chg current when the t em_timeout timer expires (enabled by default), the ucs1002 will accept that th is is the correct charger emulation profile for the attached portable device. charging commences. the resistive short between the dpout and dmout pins will be left in place. the ucs 1002 will use constant current limiting. 4. if the portable device does not draw more than i bus_chg current when t em_timeout timer expires, the ucs1002 will stop the legacy 2 charger emulati on. this will cause resistive short between the dpout and dmout pins to be removed. emulation reset occurs, and the ucs1002 will initiate the next charger emulation profile. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 66 smsc ucs1002 datasheet 9.11.3 legacy 1, 3, 4, and 6 charger emulation profiles legacy 1, 3, 4, and 6 charger em ulation profiles follow the same pattern of operation although the voltage that is applied on the dpout and dmout pins will vary. they do the following: 1. the ucs1002 will apply a voltage on the dpout pin using either a current-limited voltage source or a voltage divider between vbus and ground with the center tap on the dpout pin. 2. the ucs1002 will apply a possibly different voltage on the dmout pin using either a current- limited voltage source or a voltage divider between vbus and ground with the center tap on the dmout pin. 3. vbus voltage is applied. 4. if the portable device draws more than i bus_chg current when the t em_timeout timer expires, the ucs1002 will accept that the currently applied prof ile is the correct charger emulation profile for the attached portable device. charging comm ences. the voltages applied to the dpout and dmout pins will remain in place (unless leave_emu_resp is set to 0b). the ucs1002 will begin operating in trip mode or cc mode as determined by the i bus_r2min setting (see section 10.14, "current limiting beha vior configuration registers" ). 5. if the portable device does not draw more than i bus_chg current when t em_timeout timer expires, the ucs1002 will stop the currently applied charger emulation profile. this will cause all voltages put onto the dpout and dmout pins to be removed. emulation reset occurs, and the ucs1002 will initiate the next charger emulation profile. 9.11.4 legacy 5 charger emulation profile legacy 5 charger emulation profile does the following: 1. the ucs1002 will apply 900 mv to both the dpout and the dmout pins. 2. vbus voltage is applied. 3. if the portable device draws more than i bus_chg current when the t em_timeout timer expires, the ucs1002 will accept that the currently applied prof ile is the correct charger emulation profile for the attached portable device. charging comm ences. the voltages applied to the dpout and dmout pins will remain in place (unless leave_emu_resp is set to 0b). the ucs1002 will begin operating in trip mode or cc mode as determined by the i bus_r2min setting (see section 10.14, "current limiting beha vior configuration registers" ). 4. if the portable device does not draw more than i bus_chg current when t em_timeout timer expires, the ucs1002 will stop the currently applied charger emulation profile. this will cause all voltages put onto the dpout and dmout pins to be removed. emulation reset occurs, and the ucs1002 will initiate the next charger emulation profile. 9.11.5 legacy 7 charger emulation profile the legacy 7 charger emulation profile does the following: 1. the ucs1002 will apply a voltage on the dpout pin using a voltage divider between vbus and ground with the center tap on the dpout pin. 2. vbus voltage is applied. 3. if the portable device draws more than i bus_chg current when the t em_timeout timer expires, the ucs1002 will accept that legacy 7 is the correct char ger emulation profile for the attached portable device. charging commences. the voltage applied to the dpout pin will remain in place (unless leave_emu_resp is set to 0b). the ucs1002 will begin operating in trip mode or cc mode as determined by the i bus_r2min setting (see section 10.14, "current limiting behavior configuration registers" ). programmable usb port power controller with charger emulation datasheet smsc ucs1002 67 revision 1.4 (07-16-13) datasheet 4. if the portable device does not draw more than i bus_chg current when t em_timeout timer expires, the ucs1002 will stop the legacy 7 charger emulation profile. this will cause the voltage put onto the dpout pin to be removed. emulation reset occurs, and the ucs1002 will initiate the next charger emulation profile. 9.12 custom charger emulation profile the ucs1002 allows the user to cr eate a custom charger emulation pr ofile to handshake as any type of charger. this profile can be included in the dce cycl e. in addition, it can be placed first or last in the profile sequence in the dce cycle. see section 10.13.1, "custom emul ation configuration - 40h" . the custom charger emulation profil e uses a number of registers to define stimuli and behaviors. the custom charger emulation profile uses three separate stimulus / response pairs that will be detected and applied in sequence, allowing flexibility to ?build ? any of the preloaded emulation profiles or tailor the profile to match a specific charger application. for details, see application note 24.14 ?ucs100 2 fundamentals of custom charger emulation. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 68 smsc ucs1002 datasheet chapter 10 register description the registers shown in table 10.1 are accessible through the smbus or i 2 c. an entry of ?-? indicates that the bit is not used. writing to these bits will have no effect and reading these bits will return ?0?. an entry of res indicates that the bit is reserv ed. writing to a res bit may cause unexpected results and reading from a res bit will return either ?1? or ?0? as indicated in the bit description. while in the sleep state, the ucs1002 will retain configuration and charge rationing data as indicated in the text. if a register does not indicate th at data will be retained in the sleep power state, this information will be lost when the ucs1002 ent ers the sleep power state. table 10.1 register set in hexadecimal order register address r/w register name function default value page 00h r current measurement stores the current measurement 00h page 71 01h r total accumulated charge high byte stores the total accumulated charge delivered high byte 00h page 72 02h r total accumulated charge middle high byte stores the total accumulated charge delivered middle high byte 00h page 72 03h r total accumulated charge middle low byte stores the total accumulated charge delivered middle low byte 00h page 72 04h r total accumulated charge low byte stores the total accumulated charge delivered low byte 00h page 72 0fh r other status indicates emulation status as well as the alert# and a_det# pin status 00h page 73 10h see te x t interrupt status indicates why alert# pin asserted. 00h page 73 11h r / r-c general status indicates general status 00h page 73 12h r profile status 1 indicates which charger emulation profile was accepted 00h page 73 13h r profile status 2 00h page 73 14h r pin status indicates the pin states of the internal control pins 00h page 73 15h r/w general configuration controls basic functionality 01h page 78 16h r/w emulation configuration controls emulation functionality 8ch page 78 17h r/w switch configuration controls advanced switch functions 04h page 78 18h r/w attach detect configuration controls attach detect functionality 46h page 78 programmable usb port power controller with charger emulation datasheet smsc ucs1002 69 revision 1.4 (07-16-13) datasheet 19h r/w current limit controls th e maximum current limit 00h page 82 1ah r/w charge rationing threshold high byte controls the cu rrent threshold i thresh used by the charge rationing circuitry ffh page 83 1bh r/w charge rationing threshold low byte controls the cu rrent threshold i thresh used by the charge rationing circuitry ffh page 83 1ch r/w auto-recovery configuration controls the auto-recovery functionality 2ah page 84 1eh r/w ibus_chg configuration stores the limit for i bus_chg used to determine if emulation is successful 04h page 85 1fh r/w tdet_charge configuration stores bits that define the tdet_charge time 03h page 85 20h r/w bcs emulation enable enables bcs charger emulation profiles 06h page 87 21h r/w legacy emulation enable enables legacy charger emulation profiles 00h page 87 22h r/w bcs emulation timeout config controls timeout for each bcs charger emulation profile 10h page 88 23h r/w legacy emulation timeout config 1 controls timeout for legacy charger emulation profiles 1 - 4 b0h page 88 24h r/w legacy emulation timeout config 2 controls timeout for legacy charger emulation profiles 5 - 7 04h page 88 25h r/w high-speed switch configuration controls when the high-speed switch is enabled 14h page 78 30h r applied charger emulation indicates which charger emulation profile is being applied 00h page 90 31h r preloaded emulation stimulus 1 - config 1 indicates the stimulus and timing for stimulus 1 00h page 90 32h r preloaded emulation stimulus 1 - config 2 indicates the response and magnitude for stimulus 1 00h page 90 33h r preloaded emulation stimulus 1 - config 3 indicates the threshold and pull-up / pull-down settings for stimulus 1 00h page 90 34h r preloaded emulation stimulus 1 - config 4 indicates the resistor ratio for stimulus 1 00h page 90 35h r preloaded emulation stimulus 2 - config 1 indicates the stimulus and timing for stimulus 2 00h page 90 36h r preloaded emulation stimulus 2 - config 2 indicates the response and magnitude for stimulus 2 00h page 90 table 10.1 register set in hexadecimal order (continued) register address r/w register name function default value page programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 70 smsc ucs1002 datasheet 37h r preloaded emulation stimulus 2 - config 3 indicates the threshold and pull-up / pull-down settings for stimulus 2 00h page 90 38h r preloaded emulation stimulus 2 - config 4 indicates the resistor ratio for stimulus 2 00h page 90 39h r preloaded emulation stimulus 3 - config 1 indicates the stimulus and timing for stimulus 3 (cdp only) 00h page 90 3ah r preloaded emulation stimulus 3 - config 2 indicates the response and magnitude for stimulus 3 (cdp only) 00h page 90 3bh r preloaded emulation stimulus 3 - config 3 indicates the threshold and pull-up / pull-down settings for stimulus 3 (cdp only) 00h page 90 40h r/w custom emulation config controls general configuration of the custom charger emulation profile 01h page 99 41h r/w custom stimulus / response pair 1 - config 1 sets the stimulus and timing for stimulus 1 00h page 99 42h r/w custom stimulus / response pair 1 - config 2 sets the response and magnitude for stimulus 1 00h page 99 43h r/w custom stimulus / response pair 1 - config 3 sets the threshold and pull-up / pull-down settings for stimulus 1 00h page 99 44h r/w custom stimulus / response pair 1 - config 4 sets the resistor ratio for stimulus 1 00h page 99 45h r/w custom stimulus / response pair 2 - config 1 sets the stimulus and timing for stimulus 2 00h page 99 46h r/w custom stimulus / response pair 2 - config 2 sets the response and magnitude for stimulus 2 00h page 99 47h r/w custom stimulus / response pair 2 - config 3 sets the threshold and pull-up / pull-down settings for stimulus 2 00h page 99 48h r/w custom stimulus / response pair 2 - config 4 sets the resistor ratio for stimulus 2 00h page 99 49h r/w custom emulation stimulus 3 - config 1 sets the stimulus and timing for stimulus 3 00h page 99 table 10.1 register set in hexadecimal order (continued) register address r/w register name function default value page programmable usb port power controller with charger emulation datasheet smsc ucs1002 71 revision 1.4 (07-16-13) datasheet during power-on reset (por), the default values ar e stored in the registers. a por is initiated when power is first applied to the part and the voltage on the vdd supply surpasses the v dd_th level as specified in the electrical charac teristics. any reads to undefined registers will return 00h. writes to undefined registers will not have an effect. when a bit is ?set?, this means that the user writes a logic ?1? to it. when a bit is ?cleared?, this means that the user writes a logic ?0? to it. 10.1 current measu rement register the current measurement register stores the measured current valu e delivered to the portable device (ibus). this value is updated continuously while the de vice is in the active power state. the bit weights are in ma and the range is from 9.76 ma to 2.5 a. this data will be cleared when the device enters th e sleep or detect states. this data will also be cleared whenever the port power switch is turned of f (including during emulation or any time that vbus is discharged). 4ah r/w custom stimulus / response pair 3 - config 2 sets the response and magnitude for stimulus 3 00h page 99 4bh r/w custom stimulus / response pair 3 - config 3 sets the threshold and pull-up / pull-down settings for stimulus 3 00h page 99 4ch r/w custom stimulus / response pair 3 - config 4 sets the resistor ratio for stimulus 3 00h page 99 50h r applied current limiting behavior indicates the applied current limiting behavior 82h page 102 51h r/w custom current limiting behavior config controls the custom current limiting behavior 82h page 102 fdh r product id stores a fixed value that identifies each product 4eh page 103 feh r manufacturer id stores a fixed value that identifies smsc 5dh page 104 ffh r revision stores a fixed value that represents the revision number 82h page 104 table 10.2 current measurement register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 00h r current measurement 1249.3 624.6 312.3 156.2 78.1 39.0 19.5 9.76 00h table 10.1 register set in hexadecimal order (continued) register address r/w register name function default value page programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 72 smsc ucs1002 datasheet 10.2 total accumulated charge registers the total accumulated charge registers store the total accumulated charge delivered from the vs source to a portable device. the bit weighting of t he registers is given in ma-hrs. the register value is reset to 00_00h only when the ration_rst bit is set or if the ration_en bit is cleared. this value will be retained when the device transitions out of the active state and resumes accumulation if the device returns to the active state and charge rationing is still enabled. these registers are updated every one (1) second while the ucs1002 is in the active power state. every time the value is updated, it is compared against the target value in the charge rationing threshold registers (see section 10.6 ). this data is retained in the sleep state. table 10.3 total accumulated charge registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 01h r total accumulated charge high byte 90968 45484 22742 11371 5685 2843 1421 710.7 00h 02h r total accumulated charge middle high 355.4 177.7 88.84 44.42 22.21 11.10 5 5.552 2.776 00h 03h r total accumulated charge middle low byte 1.388 0.694 0 0.347 0 0.173 5 0.086 76 0.0 434 0.0 2169 0.01 084 00h 04h r total accumulated charge low byte 0.00 5422 0.00 271 ------00h programmable usb port power controller with charger emulation datasheet smsc ucs1002 73 revision 1.4 (07-16-13) datasheet 10.3 status registers the status registers store bits that indicate error conditions as well as attach detection and removal detection. unless otherwise noted, these bi ts will operate as described when the ucs1002 is operating in stand-alone mode. 10.3.1 other status - 0fh bit 5 - alert_pin - reflects the status of the aler t# pin. when set, indicates that the alert# pin is asserted low. this bit is set and cl eared as the alert# pin changes states. bit 4 - adet_pin - reflects the status of the a_de t# pin. when set, indicates that the a_det# pin is asserted low. this bit is set and cl eared as the a_det# pin changes states. application note: if s0 is '1', pwr_en is ena bled, and vs is not present, th e adet_pin bit will cycle if the current draw exceeds the current capacity of the bypass switch. bit 3 - chg_act - this bit is automatically set when ibus > i bus_chg and cleared when ibus < i bus_chg . application note: the chg_act bit does not indicate that a por table device has accepted one of the charger emulation profiles. this bit will cycle durin g the dedicated charger emulation cycle. bit 2 - em_act - indicates that the ucs1002 is in the active state and emulating. the actual profile that is being applied is identified by pre_em_sel[3:0] (see section 10.12.1, "applied charger emulation - 30h" ). this bit is set and cleared automatically. application note: the em_act bit does not indicate that a portable device has accepted one of the emulation profiles. this bit will cycle during th e dedicated charger emulation cycle. bits 1 - 0 - em_step[1:0] - indica tes which stimulus / response pair is currently being applied by the charger emulation profile as shown in ta b l e 1 0 . 5 . these bits are set and cleared automatically. note table 10.4 status registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 0fh r other status - - alert _pin adet_ pin chg _act em _act em_step[1:0] 00h 10h see te x t interrupt status err disch arge_ err reset min_ keep_ out tsd over _volt back_ volt over _lim 00h 11h r / r-c general status ration - - cc_ mode treg low_ cur rem att 00h 12h r profile status 1 no_ hs - - vs_lo w cust dcp cdp pt 00h 13h r profile status 2 - lg7 lg6 lg5 lg4 lg3 lg2 lg1 00h 14h r pin status - pwr_ en_pi n m2_ pin m1_ pin em_ en_ pin sel_p in pwr_state [1:0] 00h programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 74 smsc ucs1002 datasheet that the legacy charger emulation profiles and th e bc1.2 dcp charger emulation profile do not use stimulus / response pair #3. 10.3.2 interrupt status - 10h bit 7 - err - indicates that an error was detected and the device has entered the error state. writing this bit to a ?0? will clear the error state and allows the device to be returned to the active state. when written to ?0? all error conditions are checked. if all error conditions have been removed, the ucs1002 returns to the active state. this bit is set automatically by the ucs1 002 when the error state is entered. regardless of the fault handling mec hanism used, if any other bit is se t in the interrupt status register (10h), the device will not leave the error state. this bit is cleared automatically by the ucs1002 if the auto-recovery fault handling functionality is active and no error conditions are detected. likewise, this bit is cl eared when the pwr_en control is disabled. ? ?0? (default) - there are no errors detected. ? ?1? - one or more errors have been detected, and the ucs1002 has entered the error state. application note: if the auto-recovery fault handling is not used , the err bit must be written to a logic '0' to be cleared. it will also be cleared when the pwr_en control is disabled. application note: note that the err bit does not necessarily reflect the alert# pin status. the alert# pin may be cleared or asserted without the err bit changing states. bit 6 - discharge_err - indicates that the ucs 1002 was unable to discharge the vbus node. this bit will be cleared when read if the error condition ha s been removed or if the err bit is cleared. this bit will cause the alert# pin to be asserted and the device to enter the error state. bit 5 - reset - indicates that the ucs1002 has just been reset and should be re-programmed. this bit will be set at power up. this bit is cleared when read or when the pwr_en control is toggled. the alert# pin is not asserted when this bit is set. this data is retained in the sleep state. bit 4 - min_keep_out - indicates that the v-i output on the vbus pins has dropped below v bus_min. this bit will be cleared when read if the error condi tion has been removed or if the err bit is cleared. this bit will cause the alert# pin to be asse rted and the device to enter the error state. bit 3 - tsd - indicates that the internal temperature has exceeded t tsd threshold and the device has entered the error state. this bit will be cleared when read if the error condition has been removed or if the err bit is cleared. this bit will cause the alert# pin to be asserted and the device to enter the error state. table 10.5 em_step bit decode em_step[1:0] stimulus / response # 10 00 none applied / waiting for current 01 #1 10 #2 1 1 #3 if applicable programmable usb port power controller with charger emulation datasheet smsc ucs1002 75 revision 1.4 (07-16-13) datasheet bit 2 - over_volt - indicates that the vs voltage has exceeded the v s_ov threshold and the device has entered the error state. this bit will be cleared when read if the error condition has been removed or if the err bit is cleared. this bit will cause t he alert# pin to be asserted and the device to enter the error state. bit 1 - back_volt - indicates that the vbus voltage has exceeded the vs or vdd voltages by more than 150 mv. this bit will be cleared when read if th e error condition has been removed or if the err bit is cleared. this bit will cause the alert# pin to be asserted and the device to enter the error state. bit 0 - over_ilim - indicates that the ibus curr ent has exceeded both the ilim threshold and the i bus_r2min threshold settings. this bit will be cleared when read if the error condition has been removed or if the err bit is cleared. this bit will cause the alert# pin to be asserted and the device to enter the error state. 10.3.3 general status - 11h bit 7 - ration - indicates that the ucs1002 has delivered the programmed amount of power to a portable device. if the ration_beh bits are set to interrupt the host, this bit will cause the alert# pin to be asserted. this bit is cleared when read. this bit is also cleared automatically when the ration_rst bit is set or the ration_en bit is cleared (see section 10.4.1, "general configuration - 15h" ). bit 4 - cc_mode - indicates that the ibus current has exceeded ilim. bit 3 - treg - indicates that the internal temperature has exceeded t reg and that the current limit has been reduced. this bit is cleared when read and will not cause the alert# pin to be asserted unless the alert_link bit is set. bit 2 - low_cur - indicates that a portable devic e has reduced its charge current to below ~6.4 ma and may be finished charging. this bit is cleared when read and will not cause the alert# pin to be asserted unless the alert_link bit is set. bit 1 - rem - indicates that a removal detection ev ent has occurred and there is no longer a portable device present. this bit is cleared when read and will not cause the aler t# pin to be asserted. it will cause the a_det# pin to be released. bit 0 - att - indicates that an attach detection event has occurred and there is a new portable device present. this bit is cleared when read and will not ca use the alert# pin to be asserted. it will cause the a_det# pin to be asserted. 10.3.4 profile status 1 - 12h these bits are indicators only and will not cause the alert# pin or a_det# pin to change states. the cust, dcp, cdp, and pt bits are cleared under the following circumstances: the pwr_en control is disabled, a new active mode is se lected, or a removal detection event occurs. bit 7 - no_hs - the no_hs bit is only set duri ng the dedicated charger emulation cycle (see section 9.10, "no handshake" ). this bit is automatically cleared w henever a new charger emulation profile is applied. application note: the no_hs bit does not indicate that a portab le device is drawing current and it may be cleared to ?0? (indicating a handshake) and a portable device not charge. this bit is set at the end of each charger emulation profile if a portable device does not handshake with it. this bit will not be set at the same time that any other profile status register bits are set. bit 4 - vs_low - indicates that the vs voltage is below the v s_uvlo threshold and the port power switch is held off. this bit is cleared automatically when the vs voltage is above the v s_uvlo threshold. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 76 smsc ucs1002 datasheet bit 3 - cust - indicates that the portable device successfully performed a handshake with the user- defined custom charger emulation profile during th e dce cycle and is charging. based on the custom charger emulation profile configuration, the high-speed switch will be either open or closed (see section 10.13, "custom emulation configuration registers" ). the port power sw itch current limiting mode is determined by the custom curre nt limiting behavior settings (see section 10.14.2, "custom current limiting behavior configuration - 51h" ). bit 2 - dcp - indicates that the portable device ac cepted the bc1.2 dcp charge r emulation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5, "high- speed switch configuration - 25h" ), and the port power switch wil l use constant current limiting. bit 1 - cdp - indicates that the portable device successfully performed a handshake with the bc1.2 cdp charger emulation profile and is charging. t he high-speed switch will be closed, and the port power switch will use trip current limiting. bit 0 - pt - indicates that the ucs1002 is in th e data pass-through or bc1.2 sdp active mode. the high-speed switch will be closed, and the port power switch will use trip current limiting. application note: when the ucs1002 is configured as a data pass-through and a removal event and then an attach event occur without changing the ac tive mode, the pt bit will not be set again even though the ucs1002 is still operating as a data pass-through as configured. toggling the m1 control will re-enable the pt status bit. 10.3.5 profile status 2 - 13h these bits indicate which profile was accepted. thes e bits are indicators only and will not cause the alert# pin or a_det# pin to change states . these bits are cleared under the following circumstances: the pwr_en contro l is disabled, a new active mode is selected, or a removal detection event occurs. bit 6 - lg7 - indicates that the portable device successfully performed a handshake with the legacy 7 charger emulation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5, "high-speed switch configuration - 25h" . the port power switch current limiting mode is determined by the custom curre nt limiting behavior settings (see section 10.14.2, "custom current limiting behavior configuration - 51h" ). bit 5 - lg6 - indicates that the portable device successfully performed a handshake with the legacy 6 charger emulation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5, "high-speed switch configuration - 25h" ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2, "custom current limiting behavior configuration - 51h" ). bit 4 - lg5 - indicates that the portable device successfully performed a handshake with the legacy 5 charger emulation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5, "high-speed switch configuration - 25h" ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2, "custom current limiting behavior configuration - 51h" ). bit 3 - lg4 - indicates that the portable device successfully performed a handshake with the legacy 4 charger emulation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5, "high-speed switch configuration - 25h" ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2, "custom current limiting behavior configuration - 51h" ). bit 2 - lg3 - indicates that the portable device successfully performed a handshake with the legacy 3 charger emulation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5, "high-speed switch configuration - 25h" ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2, "custom current limiting behavior configuration - 51h" ). programmable usb port power controller with charger emulation datasheet smsc ucs1002 77 revision 1.4 (07-16-13) datasheet bit 1 - lg2 - indicates that the portable device successfully performed a handshake with the legacy 2 charger emulation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5, "high-speed switch configuration - 25h" ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2, "custom current limiting behavior configuration - 51h" ). bit 0 - lg1 - indicates that the portable device successfully performed a handshake with the legacy 1 charger emulation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5, "high-speed switch configuration - 25h" ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2, "custom current limiting behavior configuration - 51h" ). 10.3.6 pin status register - 14h the pin status register reflects the current pin state of the external control pins as well as identifying the power state. these bits are linked to the x_set bits (see section 10.4.3 ). bit 6 - pwr_en_pin - reflects the pwr_en control state. this bit is set and cleared automatically as the pwr_en pin / pwr_en_set bit state changes. bit 5 - m2_pin - reflects the m2 pin state. this bit is set and cleared automatically as the m2 pin / m2_set state changes. bit 4 - m1_pin - reflects the m1 pin state. this bit is set and cleared automatically as the m1 pin / m1_set state changes. bit 3 - em_en_pin - reflects the em_en pin state. this bit is set and cleared automatically as the em_en pin / em_en_set state changes. bit 2 - sel_pin - reflects the polarity settings de termined by the sel pin decode. this bit is set or cleared automatically upon device pow er-up as the sel pin is decoded. ? ?0? - the pwr_en control is active low. ? ?1? - the pwr_en control is active high. bits 1 - 0 - pwr_state[1:0] - indicates the current power state as shown in ta b l e 1 0 . 6 . these bits are set and cleared automatically as the power state changes. application note: accessing the smbus / i 2 c causes the ucs1002 to leave the sleep state. as a result, the pwr_state[1:0] bits will never read as 00b. table 10.6 pwr_state bit decode pwr_state[1:0] power state 10 0 0 sleep 01 detect 10 active 1 1 error programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 78 smsc ucs1002 datasheet 10.4 configuration registers the configuration registers contro l basic device functionality. 10.4.1 general configuration - 15h the contents of this register are retained in sleep. bit 7 - alert_mask - disables the alert# pi n from asserting in the case of an error. ? ?0? (default) - the alert# pin will be asserted if an error condition or indi cator event is detected. ? ?1? - the alert# pin will not be asserted in the event of an error condition. bit 5 - alert_link - links the alert# pin to be asserted when the low_cur and/or treg bits are set. ? ?0? (default) - the alert# pin will not be asserted if the low_cur or treg indicator bit is set. ? ?1? - the alert# pin will be asserted if the low_cur or treg indicator bit is set. bit 4 - discharge - forces the vbus to be reset and discharged when the ucs1002 is in the active state. writing this bit to a logic ?1? will cause the port power switch to be opened and the discharge circuitry to activate to discharge vbus. the port power switch will remain open while this bit is ?1?. this bit is not self-clearing. bit 3 - ration_en - enables charge rationing functionality and power monitoring. ? ?0? (default) - charge rationing is disabled. the total accumulated charge registers will be cleared to 00_00h and current data will no longer be accumulated. if the total accumulated charge registers have already reached the charge rationing threshold (see section 10.6, "charge rationing threshold registers" ), the applied response will be removed as if the charge rationing had been reset. this will also clear the ration status bit (if set). ? ?1? - charge rationing is enabled (see section 7.5, "battery full" ). bit 2 - ration_rst - resets the charge rationing functionality. when this bit is set to ?1?, the total accumulated charge registers are reset to 00_00h. in ad dition, when this bit is set, the ration status bit will be cleared and, if there are no other errors or active indicators, the alert# pin will be released. table 10.7 configuration registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 15h r/w general configuration alert_ mask -alert _link disch arge ration _en ration _rst ration_beh [1:0] 01h 16h r/w emulation configuration dis_to - - em_ti meou t_dis em_r etry leave_ emu _resp em_reset_ time[1:0] 8ch 17h r/w switch configuration pin_ig nore -em_ en_ set m2_ set m1_ set s0_ set pwr_ en_ set latch _set 04h 18h r/w attach detect configuration 0 1 0 0 dischg_time_ sel[1:0] att_th[1:0] 46h 25h r/w high-speed switch configuration ---1hsw_c ust hsw_ cdp hsw_ det hsw_ dce 14h programmable usb port power controller with charger emulation datasheet smsc ucs1002 79 revision 1.4 (07-16-13) datasheet bits 1 - 0 - ration_beh[1:0] - controls the behavior when the power rationing threshold is reached as shown in table 7.1 . 10.4.2 emulation configuration - 16h the contents of this register are retained in sleep. bit 7 - dis_to - disables the timeou t and idle reset functionality (see section 4.2.1.6, "smbus timeout and idle reset" ). ? ?0? - the timeout and idle reset functionality is enabled. ? ?1? (default) - the timeout and idle reset f unctionality is disabled. this is used for i 2 c compliance. bit 4 - em_timeout_dis - disables the emulation ci rcuitry timeout for all charger emulation profiles in the dce cycle. there is a separate bit to e nable / disable the emulation timeout for the custom charger emulation profile ( section 10.13.1, "custom emulation configuration - 40h" ); however, if the em_timeout_dis bit is set, the emulation timeout will also be disabled for the custom charger emulation profile. application note: if the em_timeout_dis bit is set and the legacy 1, legacy 3, or custom charger emulation profiles were accepted during the dce cycle, a remo val is not detected. to avoid this issue, re-enable the emulation timeout af ter applying any test profiles and charging with the 'final' profile. ? ?0? (default) - emulation timeout is enabled du ring the dedicated charger emulation cycle. an individual charger emulation profile will be applied and maintained for the duration of the t em_timeout value. when this timer expires, the ucs1002 will determine whether the charger emulation profile was successful and take appropriate action. ? ?1? - emulation timeout is disabled during the dc e cycle. the applied charger emulation profile will not exit as a result of an emulation timeout event. the i bus current will be checked continuously and if it exceeds the i bus_chg threshold for any reason, the ch arger emulation profile will be accepted. bit 3 - em_retry - configures whether the dce cycl e will reset and restart if it reaches the final profile without the portable device drawing charging current and accepting one of the profiles. this bit is only used if the ucs1002 is conf igured to emulate a dedicated charger. ? ?0? - once the dce cycle is completed, it will not restart. the dpout and dmout will be left as high-z pins and the port power switch will be cl osed. the current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2, "custo m current limiting behavior configuration - 51h" ). ? ?1? (default) - once the dce cycle is completed, it will perform emulation reset and restart from the first enabled charger emulati on profile in the dce cycle. bit 2 - leave_emu_resp - enables the dedicated charger emulation cycle mode to hold the dpout and dmout stimulus response after the ucs1002 has finished emulation using the legacy, bc1.2 dcp, or custom charger emulation profiles. application note: if the hsw_dce bit is set, the high-speed s witch will be closed regardless of the status of the leave_emu_resp bit. leaving the emulation response applied will not allow normal usb traffic. therefore, prior to setting th e hsw_dce bit, this bit should be cleared. ? ?0? - the dedicated emulation circuitry will behave no rmally. it will remove the short condition when the t em_timeout timer has expired regardless if the portable device has drawn charging current or not. ? ?1? (default) - if a portable device begins dr awing charging current while the ucs1002 is applying the bc1.2 dcp, custom, or any of the legacy ch arger emulation profiles during the dce cycle, the last response applied will be kept in place until a removal detection event occurs, the internal programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 80 smsc ucs1002 datasheet temperature exceeds the t reg value, or emulation is restarted. in the case of the bc1.2 dcp or legacy 2 charger emulation profiles, this will be the short (r dcp_res ). in the case of the legacy 1, or legacy 3 - 7 profiles, this will be the dpout and dmout pin voltages. if a portable device does not draw charging current, the dce cycle will behave normally. bits 1 - 0 - em_reset_time[1:0] - determines the length of the t em_reset time (see section 9.8.1, "emulation reset" ) as shown in table 10.8 . note 10.1 when measured, the actual emulation reset time will be t em_reset plus t discharge . 10.4.3 switch configuration - 17h the contents of this register are retained in sleep. bit 7 - pin_ignore - ignores the m1, m2, pwr_ en, and em_en pin states when determining the active mode selection and power state. ? ?0? (default) - the active mode selection and power state will be set by the or?d combination of the m1, m2, pwr_en, and em_en pin states and the corresponding bit states. ? ?1? - the active mode selection and power state w ill be set by the individual control bits and not by the m1, m2, pwr_en, and em_en pin states. these pin states are ignored. bit 5 - em_en_set - in conjunction with other cont rols, determines the active mode that is selected (see section 9.2, "active mode selection" ) and power state (see table 5.1, "power states control settings" ). this bit is or?d with the em_en pin. bit 4 - m2_set - in conjunction with other controls , determines the active mode that is selected (see section 9.2 ) and power state (see table 5.1 ). this bit is or?d with the m2 pin. bit 3 - m1_set - in conjunction with other controls , determines the active mode that is selected (see section 9.2 ) and power state (see table 5.1 ). this bit is or?d with the m1 pin. bit 2 - s0_set - in smbus mode, enables the attach and removal detection feature and affects the power state (see section 5.3.6, "s0 input" ). ? ?0? - detection is not enabled. also see table 5.1, "power states control settings" . ? ?1? (default) - detection is enabled. also see ta b l e 5 . 1 . bit 1 - pwr_en_set - controls whether the port power switch may be turned on or not and affects the power state (see section 5.3.4, "pwr_en input" ). this bit is or?d with the pwr_en pin and the polarity of both are controlled by sel pin decode. thus, if the polarity is set to active high, either the pwr_en pin or this bit must be ?1? to enable the port power switch. table 10.8 em_reset_time bit decode em_reset_time[1:0] t em_reset time (see note 10.1 ) 10 0 0 50 ms (default) 01 75ms 10 125ms 11 175ms programmable usb port power controller with charger emulation datasheet smsc ucs1002 81 revision 1.4 (07-16-13) datasheet bit 0 - latch_set - in smbus mode, controls the faul t handling routine that is used in the case that an error is detected (see section 5.3.5, "latch input" ). ? ?0? (default) - the ucs1002 will automatically re try when an error condition is detected. ? ?1? - the ucs1002 will latch its error conditions. in order for the device to return to normal active state, the err bit must be cleared by the user. 10.4.4 attach detection configuration - 18h the contents of this register are retained in sleep. bit 7 - reserved - do not change. this bit will read ?0? and should not be written to a logic ?1?. bit 6 - reserved - do not change. this bit will read ?1? and should not be written to a logic ?0?. bit 5 - reserved - do not change. this bit will read ?0? and should not be written to a logic ?1?. bit 4 - reserved - do not change. this bit will read ?0? and should not be written to a logic ?1?. bits 3 - 2 - dischg_tim e_sel[1:0] - sets the t discharge time as shown in ta b l e 1 0 . 9 . bits 1 - 0 - att_th[1:0] - determines the attach detection threshold (i det_qual ) and removal detection thresholds (i rem_qual_det and i rem_qual_act ) as shown in table 10.10 . application note: the removal threshold is different when oper ating in the active power state versus when operating in the detect power state. table 10.9 discharge time options dischg_time_sel[1:0] t discharge 10 00 100ms 0 1 200 ms (default) 10 300ms 11 400ms table 10.10 attach / removal detection threshold options att_th[1:0] attach threshold / removal threshold (detect state) removal threshold (active state) 10 00 200 a100 a 01 400 a 300 a 10 800 a (default) 700 a (default) 1 1 1000 a 900 a programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 82 smsc ucs1002 datasheet 10.4.5 high-speed switch configuration - 25h the contents of this register are retained in sleep. bit 4 - reserved - this bit will default to ?1?. changing this bit will have no effect. bit 3 - hsw_cust - enables the usb high-speed data switch to be active during the custom handshake. this control is checked at the beginn ing of charger emulation. therefore, changing this control during emulation will have no immediate effect. upon restarting charger emulation (as a result of the em_retry bit being set, a removal detectio n event, or change of emulation controls), the high-speed switch will close. ? ?0? (default) - the usb high-speed data switch is disabled while the custom charger emulation profile is applied. ? ?1? - the usb high-speed data switch is enabled while the custom charger emulation profile is applied. also, if the custom charger emulation profile is accepted during the dedicated charger emulation cycle, the high-speed switch will stay closed. bit 2 - hsw_cdp - enables the usb high-speed data switch to be active during the cdp handshake. this control is checked at the begi nning of charger emulation. theref ore, changing this control during emulation will have no immediate effect. upon restar ting charger emulation (as a result of a removal detection event or change of emulation controls), the high-speed switch will close. ? ?0? - the usb high-speed data switch is disabled during the cdp handshake. ? ?1? (default) - the usb high-speed data switch is enabled during the cdp handshake. bit 1 - hsw_det - enables the usb high-speed data switch to be active during the detect power state. if the s0 control is set to ?0?, this bit is ignored. ? ?0? (default) - the usb high-speed data switch is open during the detect power state. ? ?1? - the usb high-speed data switch will be closed during the detect power state. bit 0 - hsw_dce - enables the usb high-speed data switch after the dcp c harger emulation profile or one of the legacy charger emul ation profiles was accepted during the dce cycle and the portable device is charging. this bit is ignored if the ucs1002 is not in the active state. this bit will not cause the high-speed switch to be closed during emul ation when the dcp and legacy profiles are applied, only after the dcp or a legacy charger emulation profile has been accepted. ? ?0? (default) - the usb high-speed data switch will be open. ? ?1? - the usb high-speed data switch will be closed. 10.5 current limit register the current limit register controls the ilim used by the port power switch. the default setting is based on the resistor on the comm_sel / ilim pin and this value cannot be changed to be higher than hardware set value. the contents of this register are retained in sleep. table 10.11 current limit register addrr/wregisterb7b6b5b4b3b2b1b0 default 19hr/wcurrent limit----- ilim_sw[2:0] set by comm_sel / ilim programmable usb port power controller with charger emulation datasheet smsc ucs1002 83 revision 1.4 (07-16-13) datasheet bits 2 - 0 - ilim_sw[2:0] - sets the ilim value as shown in table 10.12 . 10.6 charge rationing threshold registers the charge rationing threshold registers set the ma ximum allowed charge that will be delivered to a portable device. every time the total accumulated charge registers are updated, the value is checked against this limit. if the value meets or exce eds this limit, the ration bit is set (see section 10.4.1 ) and action taken according to the ration_beh[1:0] bits (see section 10.4.1 ). the units are in ma-hrs with a range from 0 to ~181768. the contents of this register are retained in sleep. table 10.12 ilim_sw bit decode ilim_sw[2:0] ilim 210 000 500ma 001 900ma 010 1.0a 011 1.2a 100 1.5a 101 1.8a 110 2.0a 111 2.5a table 10.13 charge rationing threshold registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 1ah r/w charge rationing threshold high byte 90968 45484 22742 11371 5685 2843 1421 710.7 ffh 1bh r/w charge rationing threshold low byte 355.4 177.7 88.84 44.42 22.21 11.105 5.552 2.776 ffh programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 84 smsc ucs1002 datasheet 10.7 auto-recovery co nfiguration register the contents of this register are retained in sleep. the auto-recovery configuration register sets t he parameters used when the auto-recovery fault handling algorithm is invoked (see section 7.6.1, "auto-recovery fault handling" ). once the auto-recovery fault handling algorithm has checked the over-temperature and back-drive conditions, it will set the ilim value to i test and then turn on the port power switch and start the t rst timer. if, after the timer has expired, the vbus voltage is less than v test , then it is assumed that a short circuit condition is present and the error state is reset. bits 6 - 4 - tcycle[2:0] - defines the delay (t cycle ) after the error state is entered before the auto- recovery fault handling algorithm is started as shown in table 10.15 . bits 3 - 2 - trst_sw[1:0] - sets the t rst time as shown in table 10.16 . table 10.14 auto-recovery configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 1ch r/w auto-recovery configuration - tcycle[2:0] trst_sw[1:0] vtst_sw[1:0] 2ah table 10.15 t cycle options tcycle [2:0] tcycle time 210 000 15ms 001 20ms 0 1 0 25 ms (default) 011 30ms 100 35ms 101 40ms 110 45ms 111 50ms table 10.16 trst_sw options trst_sw[1:0] t rst 10 00 10ms programmable usb port power controller with charger emulation datasheet smsc ucs1002 85 revision 1.4 (07-16-13) datasheet bits 1 - 0 - vtst_sw[1:0] - sets the v test value as shown in table 10.17 . 10.8 ibus_chg configuration register the ibus_chg configuration register sets the i bus_chg current value. if current greater than i bus_chg is detected flowing out of vbus, emulation is successful. the bit weights are in ma, and the range is from 9.76 ma to 156.16 ma. application note: the contents of this register are not retained in sleep. 10.9 tdet_charge conf iguration register 01 15ms 1 0 20 ms (default) 11 25ms table 10.17 vtst_sw options vtst_sw[1:0] v test 10 0 0 250 mv 0 1 500 mv 1 0 750 mv (default) 1 1 1000 mv table 10.18 ibus_chg configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 1eh r/w ibus_chg configuration ----78.139.019.59.76 04h table 10.19 tdet_charge co nfiguration register addrr/wregister b7b6b5b4b3b2b1b0 default 1fh r/w tdet_charge configuration - - - dc_temp_ set[1:0] det_charge_set [2:0] 03h table 10.16 trst_sw options (continued) trst_sw[1:0] t rst 10 programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 86 smsc ucs1002 datasheet the contents of this register are retained in sleep. the tdet_charge configurati on register controls the t dc_temp and t det_charge timing. the t dc_temp timer is started whenever the temperature exceeds treg. this timer is meant to give the system time to cool at the lower ilim setting before changing ilim again. the t det_charge timer is started whenever the vbus voltage is discharged and the bypass switch is re-activated. this timer is meant to be a delay to allow the vbus capacitor to charge before detecting an attach detection event. bits 4 - 3 - dc_temp_set[2:0] - determines the t dc_temp time as shown in table 10.20 . bits 2 - 0 - det_charge_set[2:0] - determines the t det_charge time as shown in table 10.21 . application note: if t det_charge time is increased greater than 800 ms, larger bus capacitors can be accommodated; however, with a portable device present and pwr_en disabled, a removal detection event and then another attach detection event will occur. table 10.20 dc_temp_set bit decode dc_temp_set[1:0] tdc_temp 10 0 0 200 ms (default) 01 400ms 10 800ms 1 1 1600 ms table 10.21 det_charge_set bit decode det_charge_set[2:0] tdet_ charge 210 000 200ms 001 400ms 010 600ms 0 1 1 800 ms (default) 100 1000ms 101 1200ms 110 1400ms 111 2000ms programmable usb port power controller with charger emulation datasheet smsc ucs1002 87 revision 1.4 (07-16-13) datasheet 10.10 preloaded emulatio n enable registers the preloaded emulation enable registers enable the c harger emulation profiles used by the emulation circuitry. 10.10.1 bcs emulation enable - 20h the contents of this register are retained in sleep. bit 4 - dcp_em_dis - disables the dcp charger emulatio n profile in the dce cycle. this bit is ignored if the m1, m2, and em_en control settings have selected dcp mode (see table 9.1, "active mode selection" ). ? ?0? (default) - the bc1.2 dcp ch arger emulation profile is enabl ed during the dedicated charger emulation cycle. ? ?1? - the bc1.2 dcp charger emulation profile is not enabled during the dce cycle. bit 2 - reserved - do not change. this bit will read ?1? and should not be written to a logic ?0?. bit 1 - reserved - do not change. this bit will read ?1? and should not be written to a logic ?0?. bit 0 - reserved - do not change. this bit will read ?0? and should not be written to a logic ?1?. 10.10.2 legacy emulation enable - 21h the contents of this register are retained in sleep. bit 6 - lg7_em_dis - disables the legacy 7 charger emulation profile. ? ?0? (default) - the legacy 7 charge r emulation profile is enabled. ? ?1? - the legacy 7 charger emulation profile is not enabled. bit 5 - lg6_em_dis - disables the legacy 6 charger emulation profile. ? ?0? (default) - the legacy 6 charge r emulation profile is enabled. ? ?1? - the legacy 6 charger emulation profile is not enabled. bit 4 - lg5_em_dis - disables the legacy 5 charger emulation profile. ? ?0? (default) - the legacy 5 charge r emulation profile is enabled. ? ?1? - the legacy 5 charger emulation profile is not enabled. bit 3 - lg4_em_dis - disables the legacy 4 charger emulation profile. ? ?0? (default) - the legacy 4 charge r emulation profile is enabled. table 10.22 preloaded emulation enable registers addrr/wregisterb7 b6 b5b4b3b2b1b0 default 20h r/w bcs emulation enable - - - dcp_ em_ dis - 11006h 21h r/w legacy emulation enable -lg7_ em_ dis lg6_ em_ dis lg5_ em_ dis lg4_ em_ dis lg3_ em_ dis lg2_ em_ dis lg1_ em_ dis 00h programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 88 smsc ucs1002 datasheet ? ?1? - the legacy 4 charger emulation profile is not enabled. bit 2 - lg3_em_dis - disables the legacy 3 charger emulation profile. ? ?0? (default) - the legacy 3 charge r emulation profile is enabled. ? ?1? - the legacy 3 charger emulation profile is not enabled. bit 1 - lg2_em_dis - disables the legacy 2 charger emulation profile. ? ?0? (default) - the legacy 2 charge r emulation profile is enabled. ? ?1? - the legacy 2 charger emulation profile is not enabled. bit 0 - lg1_em_dis - disables the legacy 1 charger emulation profile. ? ?0? (default) - the legacy 1 charge r emulation profile is enabled. ? ?1? - the legacy 1 charger emulation profile is not enabled. 10.11 preloaded emulation time out configuration registers the preloaded emulation timeout configuration registers control the t em_timeout setting that is applied whenever the indicated preloaded charger em ulation profile is applied during the dce cycle. these settings are not used if the em_timeout_dis bit is set. 10.11.1 bcs emulation timeout config - 22h the contents of this register are retained in sleep. bits 5 - 4 - dcp_em_timeout[1:0] - defines the t em_timeout setting, as shown in table 10.24 , that is applied when the bc1.2 dcp charger emulation profile is used during the dce cycle. default is 1.6 s (01b). bit 3 - reserved - this bit will default to ?0?. changing this bit will have no effect. bit 2 - reserved - this bit will default to ?0?. changing this bit will have no effect. bit 1 - reserved - do not change. this bit will read ?0? and should not be written to a logic ?1?. bit 0 - reserved - do not change. this bit will read ?0? and should not be written to a logic ?1?. table 10.23 preloaded emulation timeout configuration registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 22h r/w bcs emulation timeout config - - dcp_em_ timeout[1:0] 000010h 23h r/w legacy emulation timeout config 1 lg1_em_ timeout[1:0] lg2_em_ timeout[1:0] lg3_em_ timeout[1:0] lg4_em_ timeout[1:0] b0h 24h r/w legacy emulation timeout config 2 - - lg5_em_ timeout[1:0] lg6_em_ timeout[1:0] lg7_em_ timeout[1:0] 04h programmable usb port power controller with charger emulation datasheet smsc ucs1002 89 revision 1.4 (07-16-13) datasheet 10.11.2 legacy emulation timeout config 1 - 23h the contents of this register are retained in sleep. bits 7 - 6 - lg1_em_timeou t[1:0] - defines the t em_timeout setting, as shown in table 10.24 , that is applied when the legacy 1 charger emulation profile is used during the dce cycle. default is 6.4 s (10b). bits 5 - 4 - lg2_em_timeou t[1:0] - defines the t em_timeout setting, as shown in table 10.24 , that is applied when the legacy 2 charger emulation profile is used during the dce cycle. default is 12.8 s (11b). bits 3 - 2 - lg3_em_timeou t[1:0] - defines the t em_timeout setting, as shown in table 10.24 , that is applied when the legacy 3 charger emulation profile is used during the dce cycle. default is 0.8 s (00b). bits 1 - 0 - lg4_em_timeou t[1:0] - defines the t em_timeout setting, as shown in table 10.24 , that is applied when the legacy 4 charger emulation profile is used during the dce cycle. default is 0.8 s (00b). 10.11.3 legacy emulation timeout config 2 - 24h the contents of this register are retained in sleep. bits 5 - 4 - lg5_em_timeou t[1:0] - defines the t em_timeout setting, as shown in table 10.24 , that is applied when the legacy 5 charger emulation profile is used during the dce cycle. default is 0.8 s (00b). bits 3 - 2 - lg6_em_timeou t[1:0] - defines the t em_timeout setting, as shown in table 10.24 , that is applied when the legacy 6 charger emulation profile is used during the dce cycle. default is 1.6 s (01b). bits 1 - 0 - lg7_em_timeou t[1:0] - defines the t em_timeout setting, as shown in table 10.24 , that is applied when the legacy 7 charger emulation profile is used during the dce cycle. default is 0.8 s (00b). table 10.24 x_em_timeout bit decode x_em_timeout[1:0] t em_timeout applied 10 00 0.8s 01 1.6s 10 6.4s 11 12.8s programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 90 smsc ucs1002 datasheet 10.12 preloaded emulation configuration registers table 10.25 preloaded emulation configuration registers addrr/wregisterb7 b6 b5b4b3b2b1b0 default 30h r applied charger emulation - - - - pre_em_sel[3:0] 00h 31h r preloaded emulation stimulus 1 - config 1 -s1_td _type s1_td[2:0] stim1[2:0] 00h 32h r preloaded emulation stimulus 1 - config 2 s1_r1mag[3:0] s1_r1[3:0] 00h 33h r preloaded emulation stimulus 1 - config 3 - - s1_pupd[1:0] s1_th[3:0] 00h 34h r preloaded emulation stimulus 1 - config 4 - - - - - s1_ratio[2:0] 00h 35h r preloaded emulation stimulus 2 - config 1 -s2_td _type s2_td[2:0] stim2[2:0] 00h 36h r preloaded emulation stimulus 2 - config 2 s2_r2mag[3:0] s2_r2[3:0] 00h 37h r preloaded emulation stimulus 2 - config 3 - - s2_pupd[1:0] s2_th[3:0] 00h 38h r preloaded emulation stimulus 2 - config 4 - - - - - s2_ratio[2:0] 00h 39h r preloaded emulation stimulus 3 - config 1 -s3_td _type s3_td[2:0] stim3[2:0] 00h 3ah r preloaded emulation stimulus 3 - config 2 s3_r3mag[3:0] s3_r3[3:0] 00h programmable usb port power controller with charger emulation datasheet smsc ucs1002 91 revision 1.4 (07-16-13) datasheet the preloaded emulation configurati on registers store the settings loaded from internal memory as required for the preloaded charger emul ation profile that is actively be ing applied. these registers are read only. 10.12.1 applied charger emulation - 30h the contents of this register are not retained in sleep. the contents are updated as the charger emulation profile being applied changes. bits 3 - 0 - pre_em_sel[3:0] - in dicates which of the charger emul ation profiles is being actively applied as shown in table 10.26 . 10.12.2 preloaded emulation conf iguration registers 31h - 3bh these registers store the emulatio n configuration settings for the currently applied preloaded charger emulation profile. the contents of these register s are loaded dynamically during charger emulation. when the custom charger emulation pr ofile is being applied, the cont ents of these registers will remain set at the previously applied prel oaded charger emulation profile. 3bh r preloaded emulation stimulus 3 - config 3 - - s3_pupd[1:0] s3_th[3:0] 00h table 10.26 applied emulation selection pre_em_sel[3:0] setting applied charger emulation 3210 0000data pass-through or bc1.2 sdp 0001bc1.2 cdp 0010bc1.2 dcp 0011legacy 1 0100legacy 2 0101legacy 3 0110legacy 4 0111legacy 5 1000legacy 6 1001legacy 7 1010custom profile all others not used table 10.25 preloaded emulation conf iguration registers (continued) addrr/wregisterb7 b6 b5b4b3b2b1b0 default programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 92 smsc ucs1002 datasheet application note: the legacy charger emulation profiles and the bc1.2 dcp charger emulation profile do not use the stimulus 3 configuration registers (3 9h - 3bh). whenever these charger emulation profiles are applied, registers 39h - 3bh will not be updated and their contents should be ignored. 10.12.3 preloaded emulation stimulus x - config 1 - 31h, 35h, 39h the contents of this register are not retain ed during sleep. they are updated as needed. application note: the legacy charger emulation profiles do not use these settings. whenever a legacy charger emulation profile is a pplied within the dce cycle, these controls will not be updated and should be ignored. these settings ar e only used by the bc1.2 cdp and bc1.2 dcp charger emulation profiles. bit 6 - sx_td_type - determines the behavior of the stimulus timer. ? ?0? - the stimulus timer is a delay from when the stimulus is detected until the response is performed. ? ?1? - the stimulus timer controls how long the re sponse is applied after the stimulus is detected. the response is applied immediately and held for the duration of the timer then removed (if the stimulus has been removed). bits 5 - 3 - sx_td[2:0] - determines the stimulus x t stim_del value as shown in table 10.27 . bits 2 - 0 - stimx[2:0] - determines the stimulus that is used as shown in table 10.28 . table 10.27 stimulus delay time options sx_td[2:0] setting time delay 210 000 0ms 001 1ms 010 5ms 011 10ms 100 20ms 101 40ms 110 80ms 111 100ms programmable usb port power controller with charger emulation datasheet smsc ucs1002 93 revision 1.4 (07-16-13) datasheet note 10.2 the lower threshold for the window comparator option is fixed at 400 mv and only applies to the dpout pin. this setting cannot be used for the dmout port. 10.12.4 bc1.2 emulation stimulus x - config 2 - 32h, 36h, 3ah the contents of this register are retained in sleep. bits 7 - 4 - sx_rmag[3:0] - determines the magnitude of the response to the stimulus. the bit decode changes meaning based on which response was selected as shown in table 10.30 . table 10.31 through table 10.33 show the specific de code for each function. application note: data written to any field that is identified as ?do not use? will not be accepted. the data will not be updated and the settings will re main set at the previous value. bits 3 - 0 - sx_rx[3:0] - defines the stimulus response as shown in table 10.29 . table 10.28 stimulus options stimx[2:0] setting stimulus 210 0 0 0 vbus voltage ready to be applied ( before port power switch is closed) (default). next stimulus will not wait for this stimulus to be removed. 0 0 1 dpout voltage is > threshold (sx_th). 0 1 0 window comparator. dpout voltage is < threshold (sx_th) and dpout voltage is > fixed threshold (see note 10.2 ). 0 1 1 dmout voltage is > threshold (sx_th). 1 0 0 do not use. 1 0 1 do not use. 1 1 0 dpout voltage is > threshold (sx_th). 1 1 1 vbus voltage is present (after port po wer switch is closed). next stimulus will not wait for this stimulus to be removed. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 94 smsc ucs1002 datasheet note 10.3 if stimx[2:0] = 000b and no other response was applied to the dmout pin, the 15 k pull-down resistor applied to the dmout pin during emulation reset is not removed. otherwise, the previous response is left on the dmout pin (if applicable) or the 15 k pull-down resistor is removed. note 10.4 if stimx[2:0] = 000b and no other response was applied to the dpout pin, the 15 k pull-down resistor applied to the dpout pi n during emulation reset is not removed. otherwise, the previous response is left on the dpout pin (if applicable) or the 15 k pull- down resistor is removed. table 10.29 stimulus response sx_rx[3:0] setting stimulus response 3210 0000remove previous response on dpout and dmout. 0001apply volt age on dpout (see note 10.3 ). 0010apply volt age on dmout (see note 10.4 ). 0011apply volt age on dpout and dmout. 0100connect resistor from dpout to gnd (see note 10.3 ). 0101do not use. 0110connect voltage divider from vbus to gnd with ?center? at dpout (see note 10.3 ). 0111connect resistor from dmout to gnd (see note 10.4 ). 1000do not use. 1001connect voltage divider from vbus to gnd with ?center? at dmout (see note 10.4 ). 1010connect < 200 resistor from dpout to dmout. 1011do not use. 1100connect voltage divider from vbus to gnd with ?center? at dpout. connect voltage divider from vbus to gnd with ?center? at dmout. 1101connect resistor from dpout to gnd and from dmout to gnd. 1110if stimx[2:0] = 0 00b, the 15 k pull-down resistors applied to dpout and dmout during emulation reset are not re moved. if stimx[2:0] = 111b, the 15 k pull-down resistors applied to dpout and dmout during emulation reset are removed. for all other stimx[ 2:0] settings, whatever was applied is not changed. 1111 programmable usb port power controller with charger emulation datasheet smsc ucs1002 95 revision 1.4 (07-16-13) datasheet table 10.30 response magnitude meaning response x_sx_rmag[3 :0] bit meanings 0000b - 0011b apply voltage on dpout / dmout voltage to be applied relative to ground (see table 10.33 ). 0100b, 0111b, 1101b - 1111b apply resistor on dpout / dmout to gnd or vbus magnitude of resistor (see table 10.32 ). 0110b, 1001b, 1100b apply voltage divider from vbus to gnd with ?center? at dpout / dmout minimum resistance of voltage divider from vbus to gnd (sum of r 1 + r 2 ) (see table 10.31 ). 1010b apply resistor between dpout and dmout not used. table 10.31 voltage divider minimum impedance options sx_rxmag[3:0] setting voltage divider minimum impedance options 3210 000093k 0001100k 0010125k 0011150k 0100200k 0101200k 0110200k 0111200k 100093k 1001100k 1010125k 1011150k 1100200k 1101200k 1110200k 1111do not use programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 96 smsc ucs1002 datasheet table 10.32 stimulus response resistor options sx_rxmag[3:0] setting resistor on vbus to dx_out or from dx_out to gnd 3210 00001.8k 000110k 001015k 001120k 010025k 010130k 011040k 011143k 100050k 100160k 101075k 101180k 1100100k 1101120k 1110150k 1 1 1 1 do not use table 10.33 stimulus response voltage options sx_rxmag[3:0] setting voltage on dpout / dmout 3210 0000pull-down 0001400mv 0010400mv 0011400mv 0100400mv 0101500mv 0110600mv programmable usb port power controller with charger emulation datasheet smsc ucs1002 97 revision 1.4 (07-16-13) datasheet 10.12.5 emulation stimulus x - config 3 - 33h, 37h, 3bh the contents of this register are retained in sleep. application note: the legacy charger emulation profiles do not use these settings. whenever a legacy charger emulation profile is a pplied within the dce cycle, these controls will not be updated and should be ignored. these settings are only used by the bc1.2 cdp and dcp charger emulation profiles. bits 5 - 4 - sx_pupd[1:0] - determines the magnitude of the pull-down current applied on the dpout and dmout pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (0000b). the bit decode is given in table 10.34 . bits 3 - 0 - sx_th[3:0] - defines the threshold value, as shown in table 10.35 , for the specified stimulus. if the stimulus is vbus voltage is ready to be applied or applied (i.e., stimx[2:0] = 000b or 111b), the threshold value is ignored. 0111700mv 1000800mv 1001900mv 10101400mv 10111600mv 11001800mv 11012000mv 11102200mv 1111do not use table 10.34 pull-down magnitude sx_pupd pull-down current 10 0010 a 0150 a 10100 a 11150 a table 10.33 stimulus response voltage options (continued) sx_rxmag[3:0] setting voltage on dpout / dmout 3210 programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 98 smsc ucs1002 datasheet 10.12.6 emulation stimulus x - config 4 - 34h, 38h the contents of this register are retained in sleep. application note: the bc1.2 dcp and cdp charger emulation profiles do not use this control. whenever the bc1.2 cdp or dcp charger emulation profile is applied, these controls will not be updated and should be ignored. these settings are onl y used by the legacy charger emulation profiles. bits 2 - 0 - sx_ratio[2:0] - determines the voltage divider ratio, as shown in table 10.36 , when the stimulus response is set to connect a voltage divider (i.e., sx_rx[3:0] = 0110b, 1001b, or 1100b). table 10.35 stimulus threshold values sx_th[3:0] setting voltage on dpout / dmout 3210 0000400mv 0001400mv 0010400mv 0011300mv 0100400mv 0101500mv 0110600mv 0111700mv 1000800mv 1001900mv 10101400mv 10111600mv 11001800mv 11012000mv 11102200mv 1111do not use programmable usb port power controller with charger emulation datasheet smsc ucs1002 99 revision 1.4 (07-16-13) datasheet 10.13 custom emulation co nfiguration registers table 10.36 voltage divider ratio options sx_ratiox[2:0] setting voltage divider ratio 210 0 0 0 0.25 0 0 1 0.33 0100.4 0110.5 1 0 0 0.54 1010.6 1 1 0 0.66 1 1 1 do not use table 10.37 custom emulation configuration registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 40h r/w custom emulation config --cs1_ time out_ dis cs1_em_ timeout[1:0] cs1_ first 0 cs1_ em_ dis 01h 41h r/w custom emulation stimulus 1 - config 1 - cs1_s1 _td_ type cs1_s1_td[2:0] cs1_stim1[2:0] 00h 42h r/w custom emulation stimulus 1 - config 2 cs1_s1_r1mag[3:0] cs1_s1_r1[3:0] 00h 43h r/w custom emulation stimulus 1 - config 3 - - cs1_s1_pup d[1:0] cs1_s1_th[3:0] 00h 44h r/w custom emulation stimulus 1 - config 4 - - - - - cs1_s1_ratio[2:0] 00h 45h r/w custom emulation stimulus 2 - config 1 - cs1_s2 _td_ type cs1_s2_td[2:0] cs1_stim2[2:0] 00h programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 100 smsc ucs1002 datasheet the custom emulation configurati on registers store the values used by the custom charger emulation circuitry. the custom charger emulation profile is set up as three stimuli and the respective responses. see application note 24.14 ?ucs1002 fundam entals of custom charger emulation?. 10.13.1 custom emulation configuration - 40h the contents of this register are retained in sleep. bit 5 - cs1_timeout_dis - disables the emul ation timeout timer when the custom charger emulation profile is applied during the dce cycle. if the em_timeout_dis is set, this bit will have no effect (see section 10.4.2, "emulati on configuration - 16h" ). application note: if the cs1_timeout_dis bit is set and the cu stom charger emulation profile was accepted during the dce cycle, a removal is not detected. to avoid this issue, re-enable the emulation timeout after applying any test profiles and charging with the 'final' profile. ? ?0? (default) - the emulation time out timer is enabled when the cu stom charger emulation profile is applied during the dce cycle and the em_timeout_dis bit is not set. ? ?1? - the emulation timeout timer is disabled when the custom charger emul ation profile is applied during the dce cycle. when the custom charger emulation profile is being applied, the ucs1002 will be constantly monitoring the i bus current. when the i bus current is greater than i bus_chg , 46h r/w custom emulation stimulus 2 - config 2 cs1_s2_r2mag[3:0] cs1_s2_r2[3:0] 00h 47h r/w custom emulation stimulus 2 - config 3 - - cs1_s2_pup d[1:0] cs1_s2_th[3:0] 00h 48h r/w custom emulation stimulus 2 - config 4 - - - - - cs1_s2_ratio[2:0] 00h 49h r/w custom emulation stimulus 3 - config 1 - cs1_s3 _td_ type cs1_s3_td[2:0] cs1_stim3[2:0] 00h 4ah r/w custom emulation stimulus 3 - config 2 cs1_s3_r3mag[3:0] cs1_s3_r3[3:0] 00h 4bh r/w custom emulation stimulus 3 - config 3 - - cs1_s3_pup d[1:0] cs1_s3_th[3:0] 00h 4ch r/w custom emulation stimulus 3 - config 4 - - - - - cs1_s3_ratio[2:0] 00h table 10.37 custom emulation configuration registers (continued) addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default programmable usb port power controller with charger emulation datasheet smsc ucs1002 101 revision 1.4 (07-16-13) datasheet regardless of the reason, then t he custom charger emulation profile will accepted. if the portable device does not draw more than i bus_chg current, then the ucs1002 will continue waiting until this bit is cleared. bits 4 - 3 - cs1_em_timeout[1:0] - determines the t em_timeout value, as shown in table 10.24 , that is used when the custom charger emulation profile is used during the dce cycle. bit 2 - cs1_first - determines whether the custom charger emulation profile is placed first or last in the dce cycle. ? ?0? (default) - the custom charger emulation profile is the last of the profiles applied during the dce cycle. ? ?1? - the custom charger emulation profile is the fi rst of the profiles applied during the dce cycle. bit 1 - reserved - do not change. this bit will read ?0? and should not be written to a logic ?1?. bit 0 - cs1_em_dis - disables the custom charger emulation profile. ? ?0? - the custom charger emulation profile is enabled. ? ?1? (default) - the custom charger emulation profile is not enabled. 10.13.2 custom stimulus / response pair x - config 1 - 41h, 45h, 49h the contents of this register are retained in sleep. bit 6 - cs1_sx_td_type - determines the behavior of the stimulus timer. ? ?0? - the stimulus timer is a delay from when the stimulus is detected until the response is performed. ? ?1? - the stimulus timer controls how long the re sponse is applied after the stimulus is detected. the response is applied immediately and held for the duration of the timer then removed (if the stimulus has been removed). bits 5 - 3 - cs1_sx_td[2:0] - determines the stimulus x t stim_del value as shown in table 10.27 . bits 2 - 0 - cs1_stimx[2:0] - determines the stimulus that is used as shown in table 10.28 . 10.13.3 custom stimulus / response pair x - c onfig 2 - 42h, 46h, 4ah the contents of this register are retained in sleep. bits 7 - 4 - cs1_sx_rxmag[3:0] - determines the magni tude of the response to the stimulus. the bit decode changes meaning based on which res ponse was selected as shown in table 10.30 . table 10.31 through table 10.33 show the specific decode for each function. bits 3 - 0 - cs1_sx_rx[3:0] - defines the stimulus response as shown in table 10.29 . 10.13.4 custom stimulus / response pair x - c onfig 3 - 43h, 47h, 4bh the contents of this register are retained in sleep. bits 5 - 4 - cs1_sx_pupd[1:0] - determines the magnitude of the pull-down current applied on the dpout and dmout pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (0000b). the bit decode is given in table 10.34 . bits 3 - 0 - cs1_sx_th[3:0] - defines the threshold value, as shown in table 10.35 , for the specified stimulus. if the stimulus is vbus is ready to be applied or applied (i.e., cs1_stimx[2:0] = 000b or 111b), the threshold value is ignored. programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 102 smsc ucs1002 datasheet 10.13.5 custom stimulus / response pair x - c onfig 4 - 44h, 48h, 4ch the contents of this register are retained in sleep. bits 2 - 0 - cs1_sx_ratio[2:0] - determines the voltage divider ratio, as shown in table 10.36 , when the stimulus response is set to connect a voltage divider (i.e., cs1_sx_rx[3:0] = 0110b, 1001b, or 1100b). 10.14 current limiting behavi or configuration registers 10.14.1 applied current li miting behavior - 50h this register stores the values used by the app lied current limiting mode (trip or cc) when the custom settings are not used. the contents of this register are updated automatically when charger emulation is completed. the contents of this register are not retain ed in sleep. the contents are updated as needed. bits 7 - 6 - sel_vbus_mi n[1:0] - define the v bus_min voltage as shown in table 10.39 . bits 4 - 2 - sel_r2_imin[2:0] - define the i bus_r2min current as shown in table 10.40 . bits 1 - 0 - reserved. 10.14.2 custom current limiting be havior configuration - 51h the custom current limiting behav ior configuration register allo ws programming of current limit parameters. these controls are used when a port able device handshakes using the legacy charger emulation profiles (except legacy 2), the custom c harger emulation profile, or does not handshake as a dedicated charger (i.e., a power thief). the contents of this register are retained in sleep. bits 7 - 6 - cs_vbus_min[1:0] - defines the custom v bus_min voltage as shown in table 10.39 . note that v bus_min is checked even when operating with trip current limiting. table 10.38 current limit behavior configuration registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 50h r applied current limiting behavior sel_vbus_ min[1:0] (v bus_min ) - sel_r2_imin[2:0] (i bus_r2min as shown in figure 7.2 ) 1 0 82h 51h r/w custom current limiting behavior config cs_vbus_min [1:0] (v bus_min ) - cs_r2_imin[2:0] (i bus_r2min as shown in figure 7.2 ) 1 0 82h programmable usb port power controller with charger emulation datasheet smsc ucs1002 103 revision 1.4 (07-16-13) datasheet bits 4 - 2 - cs_r2_imin[2: 0] - define the custom i bus_r2min threshold as shown in table 10.40 . the default is 100 ma. this value is used under t he following conditions: when a portable device handshakes using the legacy charger emulation prof iles (except legacy 2) or the custom charger emulation profile, or when it does not handshake in dce cycle (i.e., a power thief)). under these conditions, the current limiting mode is determined by the relative value of i bus_r2min and ilim. when i bus_r2min < ilim or ilim > 1.5 a, trip current lim iting used; otherwis e, cc mode is used. bits 1 - 0 - reserved - do not change. 10.15 product id register the product id register stores a unique 8-bit value that identifies the device. table 10.39 v bus_min threshold options x_vbus_min[1:0] v bus_min value 10 00 1.5v 0 1 1.75 v 1 0 2.0 v (default) 1 1 2.25 v table 10.40 i bus_r2min threshold options x_r2_imin[2:0] i bus_r2min value 210 000 100ma 001 500ma 010 900ma 011 1200ma 100 1500ma 101 1800ma table 10.41 product id register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default fdhr product id01001110 4eh programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 104 smsc ucs1002 datasheet 10.16 manufacturer id register the manufacturer id regist er stores a unique 8-bit va lue that identifies smsc. 10.17 revision register the revision register stores an 8-bit va lue that represents the part revision. table 10.42 manufacturer id register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default feh r manufacturer id 010111015dh table 10.43 revision register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default ffhrrevision1000001082h programmable usb port power controller with charger emulation datasheet smsc ucs1002 105 revision 1.4 (07-16-13) datasheet chapter 11 package information figure 11.1 ucs1002 package view programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 106 smsc ucs1002 datasheet figure 11.2 ucs1002 package dimensions and notes programmable usb port power controller with charger emulation datasheet smsc ucs1002 107 revision 1.4 (07-16-13) datasheet chapter 12 typical operating curves figure 12.1 usb-if high-sp eed eye diagram (without data switch) figure 12.2 usb-if high-speed eye diagram (with data switch) figure 12.3 short applied after power up figure 12.4 power up into a short figure 12.5 internal power switch short re sponse figure 12.6 vbus discharge behavior programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 108 smsc ucs1002 datasheet figure 12.7 data switch off isolation vs. frequency figure 12.8 data switch bandwidth vs. frequency figure 12.9 data switch on resistance vs. temp fi gure 12.10 power switch on resistance vs. temp figure 12.11 r dcp_res resistance vs.temp figure 12.12 power switch on / off time vs. temp programmable usb port power controller with charger emulation datasheet smsc ucs1002 109 revision 1.4 (07-16-13) datasheet figure 12.13 vs over-voltage threshold vs. temp figure 12.14 vs under voltage threshold vs. temp figure 12.15 detect state vbus vs. ibus figure 12.16 trip curre nt limit operation vs. temp. figure 12.17 ibus measurement accuracy programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 110 smsc ucs1002 datasheet figure 12.18 active state current vs. temp figure 12.19 detect state current vs. temp figure 12.20 sleep state current vs. temp programmable usb port power controller with charger emulation datasheet smsc ucs1002 111 revision 1.4 (07-16-13) datasheet chapter 13 references for additional information, the following documents are available from your smsc representative. application note 24.14 fundamental s of custom charger emulation application note 24.20 using the ucs100x or ucs8100x as a single or dual mode charger application note 25.0 ucs1002 highest current algorithm using an mcu application note 25.4 ucs1002 advanced custom charging application note 25.5 ucs1002 smart battery charger hardware reference design application note 25.7 ucs1002 charge rationing application note 25.16 usb charging port esd protection tips for ucs100x application note 26.1 - ucs1002 curr ent limit operation and features ucs1002 faqs (frequent ly asked questions) UCS1002-1 reference design ucs1001 / ucs1002 production test method charger test report programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 112 smsc ucs1002 datasheet chapter 14 document revision history table 14.1 customer revision history revision level & date section/f igure/entry correction revision 1.4 (07-16-13) cover ? added patent information to cover ? title change from ?usb port po wer controller with charger emulation? to ?programmable usb port power controller with charger emulation? ta b l e 3 . 3 , " e l e c t r i c a l specifications" ? added specifications for i det_qual / i rem_qual and i bus_chg section 9.8.2, "emulation cycling" ? updated text for dce cycle behavior. changed cycle order for 1001-3 and 1001-4. section 10.4.4, "attach detection configuration - 18h" ? changed register default setting for i det_qua l / i rem_qual default change from 45h to 46h section 10.8, "ibus_chg configuration register" ? changed register default setting for i bus_chg value change from 01h to 04h revision 1.3 (02-14-13) ta b l e 3 . 3 , " e l e c t r i c a l specifications" ? added pin wake time (t pin_wake ). ? added smbus wake time (t sbm_wake ) and idle sleep time (t idle_sleep ). ? added timeout (t timeout ) and idle reset (t idle_reset ). ? changed i sleep from 8 a (max) to 15 a (max) per characterization data. ? added 12w current limit changes. figure 5.5, "wake timing via external pins" ? changed ~3ms to t pin_wake . removed third example: ?wake with s0 & pwr_en to auto-transition detect state (vs > vs_uvlo, m1 & m2 & em_en not all ?0? and not set to data pass-through)?. figure ?wake via smbus read with s0 = ?0? ? changed >5ms to t idle_sleep . ? changed time between reads from 1ms programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 114 smsc ucs1002 datasheet table 9.2, "current limit mode options" ? rearranged rows so dce cycle is grouped together. ? added row for dce cycle when a charger emulation profile is being applied. ? for legacy charger emulation profiles 1 and 3-7 and the custom profile, the current limiting behavior used when the profile is accepted is also used if the timeout is disabled when the profile is applied during the dce cycle. ? added text below table: as noted in the last three rows in table 9.2 , under those specific conditions with ilim < 1.5 a, it is the relationship of ilim and i bus_r2min that determines the current limiting mode. in these cases, the value of i bus_r2min is determined by cs_r2_imin[2:0] bits 4-2 in the custom current limiting behavior configuration register 51h. section 9.8.2, "emulation cycling" and section 9.11.5, "legacy 7 charger emulation profile" ? legacy 7 charger emulation profile defined and enabled by default. section 10.4, "configuration registers" and table 10.10, "attach / removal detection threshold options" ? att_th[1:0] default changed from 200 a to 400 a. 18h register default changed from 44h to 45h. section 10.10.2, "legacy emulation enable - 21h" ? legacy 7 charger emulation profile enabled by default. register 21h default changed from 40h to 00h. section 10.14.2, "custom current limiting behavior configuration - 51h" ? clarified description of cs_r2_imin[2:0]. chapter 12, typical operating curves ? rearranged order of tocs. ? added new tocs: ? figure 12.3, "short applied after power up" ? figure 12.5, "internal power switch short response" ? figure 12.16, "trip current limit operation vs. temp." ? figure 12.17, "ibus measurement accuracy" ? figure 12.18, "active state current vs. temp" ? figure 12.19, "detect state current vs. temp" ? figure 12.20, "sleep state current vs. temp" ? updated the following: ? figure 12.6, "vbus discharge behavior" ? figure 12.11, "rdcp_res resistance vs.temp" ? figure 12.13, "vs over-voltage threshold vs. temp" ? figure 12.14, "vs under voltage threshold vs. temp" ? figure 12.15, "detect state vbus vs. ibus" revision 1.1 (11-21-11) table 3.2, "power dissipation summary" ? missing units added. table 14.1 customer revisi on history (continued) revision level & date section/f igure/entry correction programmable usb port power controller with charger emulation datasheet smsc ucs1002 115 revision 1.4 (07-16-13) datasheet ta b l e 3 . 3 , " e l e c t r i c a l specifications" ? changed t det_charge from 400 ms to 800 ms typ and changed condition from c bus = 220 f to c bus = 500 f max. ? vs leakage current changed from 0.8 a typical to 2.2 a. ? changed i bd_1 and i bd_2 from tbd typ to 0 a typ and from 1.5 a max to 2 a max ? changed i tst to i test and changed typ from 165 to 190 ma. ? changed t on_psw from 3 ms to 0.75 ms typical and t off_psw_ina from 1 ms to 0.75 ms typical. ? spec changed for t hd:dat . 0 s min has condition when transmitting to master. new row added with 0.3 s min with condition when receiving from master. ? new characteristic: bus free time stop to start, start setup time, hold time, setup time, clock low period, clock high period data fall time -> clock / data fall time data rise time -> clock / data rise time table 3.4, "esd ratings"section 3.1 ? charged device model: changed from 200 v to 500 v section 4.2.2 ? differences between smbus and i2c revised. note 5.1 ? added note: in order to transition from active state data pass- through mode into sleep with these settings, change the m1, m2, and em_en pins before changing the pwr_en pin. table 5.1, "power states control settings" , section 5.1.2, "sleep state operation" , section 6.1, "usb high- speed data switch" ? the high-speed switch is open in sleep. section 5.2.2, "vs source voltage" ? added. section 4.2.4 ? new section i2c protocols, covering sections block write and block read moved from section 4.2.3 . section 10.4.2, "emulation configuration - 16h" ? added application note regardin g em_timeout_dis: if the em_timeout_dis bit is set and the legacy 1, legacy 3, or custom charger emulation profiles were accepted during the dce cycle, a removal is not detected. to avoid this issue, re- enable the timeout after applying any test profiles and charging with the 'final' profile. section 10.13.1, "custom emulation configuration - 40h" ? added application note regarding cs1_timeout_dis: if the cs1_timeout_dis bit is set and the custom charger emulation profile was accepted during the dce cycle, a removal is not detected. to avoid this issue, re-enable the timeout after applying any test profiles and charging with the 'final' profile. cover, section 9.11.3, "legacy 1, 3, 4, and 6 charger emulation profiles" ? legacy 6 profile has been defined. section 10.11.3, "legacy emulation timeout config 2 - 24h" ? register 24h default changed from 00h to 04h (legacy 6 timeout 1.6 s). table 14.1 customer revisi on history (continued) revision level & date section/f igure/entry correction programmable usb port power controller with charger emulation datasheet revision 1.4 (07-16-13) 116 smsc ucs1002 datasheet revision 1.1 (11-21-11) cont. section 9.4, "data pass- through (no charger emulation)" ? data pass-through persists until m1, m2, or em_en controls are changed. it is no longer affected by pwr_en. added application note: when the m1, m2, and em_en controls are set to ?0?, ?1?, ?0? or to ?1?, ?1?, ?0? respectively, data pass- through mode will persist if the pwr_en control is disabled; however, the ucs1002 will draw more current. to leave data pass-through mode, the pwr_en control must be enabled before the m1, m2, and em_en controls are changed to the desired mode. section 9.6, "bc1.2 cdp" ? bc1.2 cdp mode uses constant current limiting. added application note: bc1.2 compliance testing may require the s0 control to be set to ?0? (attach and removal detection feature disabled) while testing is in progress. ? added application note: when the ucsx100x is in bc1.2 cdp mode and the attach and removal detection feature is enabled, if a power thief, such as a usb light or fan, attaches but does not assert dp, a removal event will not occur when the portable device is removed. however, if a standard usb device is subsequently attached, removal detection will again be fully functional. as well, if pwr_en is cycled or m1, m2, and / or em_en change state, a removal event will occur and attach detection will be reactivated. section 9.7, "bc1.2 dcp" ? added application note: bc1.2 compliance testing may require the s0 control to be set to ?0? (attach and removal detection feature disabled) while testing is in progress. table 9.2, "current limit mode options" ? bc1.2 cdp charger emulation changed from using ?trip? to ?cc mode if ilim < 1.5 a, otherwise, trip mode?. section 9.11.4, "legacy 5 charger emulation profile" ? added. the legacy 5 charger emulation profile no longer applies a voltage divider. it applies 900 mv to dpout and dmout. revision 1.0 (08-18-11) initial release table 14.1 customer revisi on history (continued) revision level & date section/f igure/entry correction |
Price & Availability of UCS1002-1
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |